X87

The x87 registers form an eight-level deep non-strict stack structure ranging from ST(0) to ST(7) with registers that can be directly accessed by either operand, using an offset relative to the top, as well as pushed and popped. (This scheme may be compared to how a stack frame may be both pushed/popped and indexed.) There are instructions to push, calculate, and pop values on top of this stack; unary operations (FSQRT, FPTAN etc.) then implicitly address the topmost ST(0), while binary operations (FADD, FMUL, FCOM, etc.) implicitly address ST(0) and ST(1). The non-strict stack model also allows binary operations to use ST(0) together with a direct memory operand or with an explicitly specified stack register, ST(x), in a role similar to a traditional accumulator (a combined destination and left operand). This can also be reversed on an instruction-by-instruction basis with ST(0) as the unmodified operand and ST(x) as the destination. Furthermore, the contents in ST(0) can be exchanged with another stack register using an instruction called FXCH ST(x). These properties make the x87 stack usable as seven freely addressable registers plus a dedicated accumulator (or as seven independent accumulators). This is especially applicable on superscalar x86 processors (such as the Pentium of 1993 and later), where these exchange instructions (codes D9C8..D9CFh) are optimized down to a zero clock penalty by using one of the integer paths for FXCH ST(x) in parallel with the FPU instruction. Despite being natural and convenient for human assembly language programmers, some compiler writers have found it complicated to construct automatic code generators that schedule x87 code effectively. Such a stack-based interface potentially can minimize the need to save scratch variables in function calls compared with a register-based interface (although, historically, design issues in the 8087 implementation limited that potential.) The x87 provides single-precision, double-precision and 80-bit double-extended precision binary floating-point arithmetic as per the IEEE 754-1985 standard. By default, the x87 processors all use 80-bit double-extended precision internally (to allow sustained precision over many calculations, see IEEE 754 design rationale). A given sequence of arithmetic operations may thus behave slightly differently compared to a strict single-precision or double-precision IEEE 754 FPU. As this may sometimes be problematic for some semi-numerical calculations written to assume double precision for correct operation, to avoid such problems, the x87 can be configured using a special configuration/status register to automatically round to single or double precision after each operation. Since the introduction of SSE2, the x87 instructions are not as essential as they once were, but remain important as a high-precision scalar unit for numerical calculations sensitive to round-off error and requiring the 64-bit mantissa precision and extended range available in the 80-bit format. Performance Clock cycle counts for examples of typical x87 FPU instructions (only register-register versions shown here). The A...B notation (minimum to maximum) covers timing variations dependent on transient pipeline status and the arithmetic precision chosen (32, 64 or 80 bits); it also includes variations due to numerical cases (such as the number of set bits, zero, etc.). The L → H notation depicts values corresponding to the lowest (L) and the highest (H) maximal clock frequencies that were available. :* An effective zero clock delay is often possible, via superscalar execution. :§ The 5 MHz 8087 was the original x87 processor. Compared to typical software-implemented floating-point routines on an 8086 (without an 8087), the factors would be even larger, perhaps by another factor of 10 (i.e., a correct floating-point addition in assembly language may well consume over 1000 cycles). ==Manufacturers==

Companies that have designed or manufactured floating-point units compatible with the Intel 8087 or later models include AMD (287, 387, 486DX, 5x86, K5, K6, K7, K8), Chips and Technologies (the Super MATH coprocessors), Cyrix (the FasMath, Cx87SLC, Cx87DLC, etc., 6x86, Cyrix MII), Fujitsu (early Pentium Mobile etc.), Harris Semiconductor (manufactured 80387 and 486DX processors), IBM (various 387 and 486 designs), IDT (the WinChip, C3, C7, Nano, etc.), IIT (the 2C87, 3C87, etc.), LC Technology (the Green MATH coprocessors), National Semiconductor (the Geode GX1, Geode GXm, etc.), NexGen (the Nx587), Rise Technology (the mP6), ST Microelectronics (manufactured 486DX, 5x86, etc.), Texas Instruments (manufactured 486DX processors etc.), Transmeta (the TM5600 and TM5800), ULSI (the Math·Co coprocessors), VIA (the C3, C7, and Nano, etc.), Weitek (the 1067, 1167, 3167 and 4167), and Xtend (the 83S87SX-25 and other coprocessors). ==Architectural generations==

8087 The 8087 was the first math coprocessor for 16-bit processors designed by Intel. It was released in 1980 to be paired with the Intel 8088 or 8086 microprocessors. (Intel's earlier 8231 and 8232 floating-point processors, marketed for use with the i8080 CPU, were in fact licensed versions of AMD's Am9511 and Am9512 FPUs from 1977 and 1979.) 80C187 Although the original 1982 datasheet for the (NMOS based) 80188 and 80186 seem to mention specific math coprocessors, both chips were actually paired with an 8087. However, in 1987, in order to work with the refreshed CMOS based Intel 80C186 CPU, Intel introduced the 80C187 math coprocessor. The 80C187 interface to the main processor is the same as that of the 8087, but its core is essentially that of an 80387SX and is thus fully IEEE 754-compliant and capable of executing all the 80387's extra instructions. 80287 The 80287 (i287), released in 1982, is the math coprocessor for the Intel 80286 series of microprocessors. Intel's models included variants with specified upper frequency limits ranging from 6 up to 12 MHz. The NMOS version were available 6, 8 and 10 MHz. The available 10 MHz Intel 80287-10 Numerics Coprocessor version was for in quantities of 100. These boxed version of 80287, 80287-8, and 80287-10 were available for $212, $326, and $374, respectively. There was boxed version of 80C287A available for $457. Other 287 models with 387-like performance are the Intel 80C287, built using CHMOS III, and the AMD 80EC287 manufactured in AMD's CMOS process, using only fully static gates. Later followed the i80287XL with 387SX microarchitecture with a 287 pinout, the i80287XLT, a special version intended for laptops, as well as other variants. It contains an internal 3/2 multiplier, so that motherboards that ran the coprocessor at 2/3 CPU speed could instead run the FPU at the same speed of the CPU. Both 80287XL and 80287XLT offered 50% better performance, 83% less power consumption, and additional instructions. The 80287 works with the 80386 microprocessor and was initially the only coprocessor available for the 80386 until the introduction of the 80387 in 1987. The 80387 is strongly preferred for its higher performance and more capable instruction set. KL Intel C80287.jpg|6 MHz version of the Intel 80287 Intel 80287 die.jpg|Intel 80287 die shot KL Intel i80287XL Big Markings.jpg|Intel 80287XL KL Intel 80287XLT.jpg|Intel 80287XLT 80387 The 80387 (387 or i387) is the first Intel coprocessor to be fully compliant with the IEEE 754-1985 standard. Released in 1987, two years after the 386 chip, the i387 includes much improved speed over Intel's previous 8087/80287 coprocessors and improved characteristics of its trigonometric functions. It was made available for USD $500 in quantities of 100. Shortly afterwards, it was made available through Intel's Personal Computer Enhancement Operation for a retail market price of USD $795. The 25 MHz version was available in retail channel for USD $1395. The Intel M387 math coprocessor met under MIL-STD-883 Rev. C standard. This device was tested which includes temperature cycling between -55 and 125 °C, hermeticity sealed and extended burn-in. This military version operates at 16 MHz. This military version was available in 68-lead PGA and quad flatpack. This military version was available for USD $1155 in 100-unit of quantities for the PGA version. The 33 MHz version of 387DX was available and it has the performance of 3.4 megawhetstones per second. The following boxed version of 16-, 20-, 25-, and 33-MHz 387DX math coprocessor were available for USD $570, $647, $814, and $994 respectively. The 8087 and 80287's FPTAN and FPATAN instructions are limited to an argument in the range ±π/4 (±45°), and the 8087 and 80287 have no direct instructions for the SIN and COS functions. Without a coprocessor, the 386 normally performs floating-point arithmetic through (relatively slow) software routines, implemented at runtime through a software exception handler. When a math coprocessor is paired with the 386, the coprocessor performs the floating-point arithmetic in hardware, returning results much faster than an (emulating) software library call. The i387 is compatible only with the standard i386 chip, which has a 32-bit processor bus. The later cost-reduced i386SX, which has a narrower 16-bit data bus, cannot interface with the i387's 32-bit bus. The i386SX requires its own coprocessor, the 80387SX, which is compatible with the SX's narrower 16-bit data bus. The 387SX coprocessor was also offered in a low-power version. Marketed as "Intel387 SL Mobile Math CoProcessor", it included power-management features which allowed it to run without significantly reducing battery life. There are two battery-saving power-down features. The first one stops the coprocessor's clock when the CPU goes into "stop clock" mode; the 387SL consumes about 25 microamperes when its clock is stopped. The second one operates automatically when the CPU is running, putting the 387SL into "idle mode" when it is not executing an instruction. When active, the 387SL typically consumes 30 percent less battery power (about 100 mA) than the 387SX. In idle mode, it consumes 4 mA, a 96 percent power reduction compared to the active mode. It works in the range of 16 to 25 MHz and does not require BIOS or hardware reconfiguration. It was initially available for USD $189. File:KL Intel 80387.jpg|i387 File:KL Intel i387SX.jpg|i387SX File:KL intel i387DX.jpg|i387DX File:Intel 387 arch.svg|i387 microarchitecture with 16-bit barrel shifter and CORDIC unit File:80386with387.JPG|i386DX with i387DX File:Socket for Intel 80387.jpg|Socket for the 80387 80487 Introduced in 1991, the i487SX (P23N) was marketed as a floating-point unit coprocessor for Intel i486SX machines. It actually contained a full-blown i486DX implementation. When installed into an i486SX system, the i487 disabled the main CPU and took over all CPU operations. The i487 manual claims that the unit would not function without an i486SX in place, but independent testing (and later Intel admission) has revealed otherwise. The i487 used a special 169-pin socket with an unconnected (physical keying) pin to prevent insertion into the regular 168-pin 486 socket. At least two sources claim that the socket is the same as Socket 1, the upgrade socket for i486 OverDrive, a processor replacement in a similar vein. The FPU instruction set of i486DX/i487SX was not different from the 387, but integration provided a bus utilisation benefit. On-chip algorithms were also improved. The RapidCAD, a 386-to-486 upgrade package marketed at computer-aided design use, also includes a dummy FPU (RapidCAD-2) that is installed on the 80387 socket for compatibility purposes, as the main processor (RapidCAD-1, a 486DX) includes an integrated FPU by default. Nx587 NexGen's Nx587 FPU for the Nx586 processor, released in 1995, was the last x87 coprocessor to be manufactured separately from the CPU. ==See also==