Once an OSPM-compatible operating system activates ACPI, it takes exclusive control of all aspects of power management and device configuration. The OSPM implementation must expose an ACPI-compatible environment to device drivers, which exposes certain system, device and processor states.
Power states Global states The ACPI Specification defines the following four global "Gx" states and six sleep "Sx" states for an ACPI-compliant computer system: The specification also defines a
Legacy state: the state of an operating system which does not support ACPI. In this state, the hardware and power are not managed via ACPI, effectively disabling ACPI.
Device states The device states
D0–
D3 are device dependent: •
D0 or
Fully On is the operating state. • As with S0ix, Intel has
D0ix states for intermediate levels on the SoC. •
D1 and
D2 are intermediate power-states whose definition varies by device. •
D3: The D3 state is further divided into
D3 Hot (has auxiliary power), and
D3 Cold (no power provided): •
Hot: A device can assert power management requests to transition to higher power states. •
Cold or
Off has the device powered off and unresponsive to its bus.
Processor states The CPU power states
C0–
C3 are defined as follows: •
C0 is the operating state. •
C1 (often known as
Halt) is a state where the processor is not executing instructions, but can return to an executing state essentially instantaneously. All ACPI-conformant processors must support this power state. Some processors, such as the
Pentium 4 and
AMD Athlon, also support an Enhanced C1 state (
C1E or Enhanced Halt State) for lower power consumption, however this proved to be buggy on some systems. •
C2 (often known as
Stop-Clock) is a state where the processor maintains all software-visible state, but may take longer to wake up. This processor state is optional. •
C3 (often known as
Sleep) is a state where the processor does not need to keep its
cache coherent, but maintains other state. Some processors have variations on the C3 state (Deep Sleep, Deeper Sleep, etc.) that differ in how long it takes to wake the processor. This processor state is optional.
Additional states are defined by manufacturers for some processors. They are reported to the system via the method. For example,
Intel's
Haswell platform has states up to
C10, where it distinguishes
core states and
package states: the difference being that the
package not only includes the processor cores, but also components such as the L3 cache, memory controller, and other I/O functions. Similarly, AMD
Zen 4 CPUs diffentiate between C-states and P-states for the core and the Data Fabric. For describing the idle states of groupings of components (e.g. a package containing several cores), the (low power idle) method is used. This should not be confused with Intel's private table, used to describe S0ix sleep in package C10 or PCH SLP_S0 state.
Performance state While a device or processor operates (D0 and C0, respectively), it can be in one of several
power-performance states. These states are implementation-dependent. P0 is always the highest-performance state, with P1 to P
n being successively lower-performance states. The total number of states is device or processor dependent, but can be no greater than 16. P-states have become known as
SpeedStep in
Intel processors, as
PowerNow! or
Cool'n'Quiet in
AMD processors, and as
PowerSaver in
VIA processors. •
P0 maximum power and frequency •
P1 less than
P0, voltage and frequency scaled •
P2 less than
P1, voltage and frequency scaled •
Pn less than
P(n–1), voltage and frequency scaled See for a brief description of a newer control method based on the ACPI Collaborative Processor Performance Control (CPPC). This new method allows hundreds of possible states, and for the processor to autonomously to choose from a given range of states. == Interfaces ==