AND-OR-invert

Most logic optimization result in a sum-of-products or product-of-sums logic expression. AOI is used for sum-of-products, the variables are ANDed to form minterms which are ORed together then inverted: • is known as an AOI 2-1 gate. • is known as an AOI 2-2 gate. • is known as an AOI 3-3 gate. • is known as an AOI 4-4 gate. • is known as an AOI 5-3-2 gate. • and other variations. ==Examples==

AOI gates perform one or more AND operations followed by an OR operation then an inversion. 2-1 AOI gate The 2-1 AOI gate can be represented by the following boolean equation and truth table: : Q = \overline{(A . B) + C}. 2-2 AOI gate Real world examples of an 2-2 AOI gate are found in the CD4085B, SN74LS51, SN5450 logic ICs (see further below). The 2-2 AOI gate can be represented by the following Boolean equation and truth table: : Q = \overline{(A \wedge B) \vee (C \wedge D)}. 3-3 AOI gate Real world examples of an 3-3 AOI gate is found in the SN74LS51 logic IC (see further below). The 3-3 AOI gate can be represented by the following Boolean equation and truth table: : Q = \overline{(A \wedge B \wedge C) \vee (D \wedge E \wedge F)}. Its logic table would have 64 entries, but is not shown. 4-4 AOI gate Real world examples of an 4-4 AOI gate is found in the CD4048B logic IC (see further below). The 4-4 AOI gate can be represented by the following Boolean equation and truth table: : Q = \overline{(A \wedge B \wedge C \wedge D) \vee (E \wedge F \wedge G \wedge H)}. Its logic table would have 256 entries, but is not shown. ==Extensions to multiple levels==

It is possible to create multi-level compound gates, which combine the logic of AND-OR-invert gates with OR-AND-invert gates. An example is shown below. The parts implementing the same logic have been put in boxes with the same color. ==Electronic implementation==

AND-OR-invert (AOI) and OAI gates can be readily implemented in CMOS circuitry. AOI gates are particularly advantaged in that the total number of transistors (or gates) is less than if the AND, NOT, and OR functions were implemented separately. This results in increased speed, reduced power, smaller area, and potentially lower fabrication cost. For example, a 2-1 AOI gate can be constructed with 6 transistors in CMOS, compared to 10 transistors using a 2-input NAND gate (4 transistors), an inverter (2 transistors), and a 2-input NOR gate (4 transistors). In NMOS logic, the lower half of the CMOS circuit is used in combination with a load device or pull-up transistor (typically a depletion load or a dynamic load). AOI gates are similarly efficient in transistor–transistor logic (TTL). ;Examples CMOS 4000-series logic family: • CD4085B = dual 2-2 AOI gate • CD4086B = single expandable 2-2-2-2 AOI gate" • CD4048B = single expandable 8-input 8-function with three-state output, 8 choices for gate type: 8 NOR / 8 OR / 8 NAND / 8 AND / 4-4 AND-OR-Invert / 4-4 AND-OR / 4-4 OR-AND-Invert / 4-4 OR-AND TTL 7400-series logic family: (in past decades, a number of AOI parts were available in the 7400 family, but currently most are obsolete (no longer manufactured)) • SN5450 = dual 2-2 AOI gate, one is expandable (SN54 is military version of SN74) • SN74LS51 = 2-2 AOI gate and 3-3 AOI gate • SN54LS54 = single 2-3-3-2 AOI gate File:Logique74ls51.svg|Schematic of SN74LS51 IC consists of a 3-3 AOI gate and 2-2 AOI gate File:Ttl inside 7451.svg|Pinout of SN74LS51 IC ==See also==