AT&T Hobbit

The C Machine Project at Bell Labs had been underway since 1975 to develop computer architectures to run C programming language programs efficiently, aiming for a design that would offer an order of magnitude performance improvement over commercially available computers while remaining competitive in terms of cost. The design methodology for the C Machine architecture involved an iterative development approach informed by measurements of C program characteristics, involving the formulation and implementation of new computer architecture revisions, the development of a compiler to target each new revision, the compilation of "a large body of UNIX software", and the analysis of the compiled software. The results from such measurements then informed subsequent architecture revisions. Following on from the stabilization of the C Machine architecture in 1981 for an uncompleted ECL implementation, a design team was formed for CRISP in April 1983, and CRISP was first produced in a silicon implementation in 1986. The performance objectives were largely met by the fabricated processor, running at 16 MHz and delivering a Dhrystone benchmark score over 13 times greater than the VAX-11/750, achieving approximately 7.7 VAX MIPS. This was competitive with the MIPS R2000 as delivered in the MIPS M/500 Development System (an 8 MHz device delivering around 7.4 VAX MIPS) although some benchmarks showed somewhat stronger performance by the CRISP processor. Compared to the R2000 which required numerous support chips when incorporated into a computer system, the CRISP was a "complete" processor incorporating on-chip caches and had "substantially" reduced board area requirements. It was introduced in 1992 in the form of the 92010 and aimed at the personal communicator market. Operating at 3.3V, its reported performance is up to 13.5 VAX MIPS. Initial pricing in multiples of 10,000 units was given as $35 per unit, with the full chipset below $100. Several support chips were produced: • AT&T 92011 System Management Unit • AT&T 92012 PCMCIA Controller • AT&T 92013 Peripheral Controller • AT&T 92014 Display Controller AT&T followed in 1993 with the 92020 family of processors, introducing new support chipsets targeting different applications. These devices can run at 3.3V or at 5V with an elevated clock frequency. The 92020S is pin-compatible with the 92010, has a larger 6 KB instruction cache (as opposed to the 3 KB cache of the 92010 The 92020S was intended to be used in conjunction with most of the original 92010 chipset, excluding the 92013 peripheral controller. Meanwhile, the 92020M and 92020MX processors were intended for use with the new support chips, also employing a multiplexed address and data bus for reduced pin count, and offering lower levels of performance, with the 92020M also utilizing a 6 KB cache and achieving similar performance to the original 92010. The updated support chips are as follows: • AT&T 92021M System Management Unit • AT&T 92021MX System Management Unit • AT&T 92024M Display Controller The most highly integrated processor, the 92020MX, preserved the 3 KB cache of the 92010 but has a single-channel PCMCIA interface and a display controller supporting resolutions of up to . Costing $32 per unit in 10,000 unit quantities, it presented opportunities for cost reduction with certain devices when compared to the original Hobbit chipset. Apple rejected the Hobbit and adopted the ARM610 for the Newton, also partnering with Acorn Computers and VLSI Technology to form Advanced RISC Machines (ARM) in late 1990 with a $2.5 million investment. Apple sold its stake in ARM years later for a net $800 million. was later purchased by AT&T and was subsumed by AT&T's Eo subsidiary, which produced an early PDA, the EO Personal Communicator, running PenPoint OS from the GO Corporation. AT&T made early announcements in 1992 of broad vendor adoption. Hobbit was used in the earliest prototypes of the BeBox until in 1993, AT&T announced discontinuation of Hobbit. AT&T closed its Eo operations which were responsible for the only commercially released product using the Hobbit, and finally discontinued the Hobbit in 1994. ==Design==

In a traditional RISC design implementing a load–store architecture, memory is accessed through instructions that explicitly load data into registers and store data back to memory, with instructions that manipulate data working solely on the registers. By seeking to limit the data processing operations to a single clock cycle, a simpler control mechanism can be employed to dispatch instructions, making it easier to tune the instruction pipelines, and add superscalar support. However, programming languages do not actually operate in this fashion. Generally they use a stack containing local variables and other information for subroutines known as a stack frame or activation record. The compiler writes code to create activation records using the underlying processor's load-store design. The C Machine in its CRISP implementation, and the Hobbit that followed directly, both aim to support the types of memory access that programming languages use, with the C programming language being a particular consideration. mapped to the address space corresponding to the top of the program stack, these being purely accessible using a stack-relative addressing mode. The CRISP architecture was described as a "2½ address memory-to-memory machine", where instructions can employ zero, one, or two memory addresses and can employ a stack entry called the accumulator for computation results. Reminiscent of the Bellmac 32 architecture, various instructions designed to support procedure calling are provided by the CRISP architecture: call saves the return address and branches to a routine; enter allocates a stack frame for a routine, flushing stack cache entries if necessary; return deallocates the stack frame and branches to the caller's return address; catch restores stack entries from memory. The VMs for Android (Dalvik), Parrot, and Lua are also register-based. ==See also==