The AVR is a modified Harvard architecture machine, where program and data are stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions.
Basic families AVRs are generally classified into following:
tinyAVR – the ATtiny series The ATtiny series features small package microcontrollers with a limited peripheral set available. However, the improved tinyAVR 0/1/2-series (released in 2016) include: • Peripherals equal to or exceed megaAVR 0-series • Event System • Improved AVRxt instruction set (improved timing of calls), hardware multiply
megaAVR – the ATmega series The ATmega series features microcontrollers that provide an extended instruction set (multiply instructions and instructions for handling larger program memories), an extensive peripheral set, a solid amount of program memory, as well as a wide range of pins available. The megaAVR 0-series (released in 2016) also has functionality such as: • Event system • New peripherals with enhanced functionality • Improved AVRxt instruction set (improved timing of calls)
AVR Dx – The AVR Dx family features multiple microcontroller series, focused on
HCI, analog signal conditioning and functional safety. The parts numbers is formatted as AVR
ffD
xpp, where
ff is flash size,
x is family, and
pp is number of pins. Example: AVR128DA64 – 64-pin DA-series with 128k flash. All devices in the AVR Dx family include: • an Async Type D timer that can run faster than the CPU • 12-bit ADC • 10-bit DAC •
AVR DA-series (early 2020) – The high memory density makes these MCUs well suited for both wired and wireless communication-stack-intensive functions. • integrated sensors for capacitative touch measurement (
HCI) • updated core independent peripherals (
CIPs) and analog peripherals • no external high frequency crystal •
AVR DB-series (mid-late 2020) – inherits many features from the DA-family, while adding its own: • 2 or 3 on-chip opamps • MultiVoltage IO (MVIO) on PORTC • Supports external HF crystal •
AVR DD-series • 16–64 KiB Flash • 2–8 KiB SRAM • 14–32-pin package • internal 24 MHz oscillator • 7–23-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC) • no amplifiers • 1 analog comparator • Two USARTs, one SPI, one dual-mode TWI • Multi-Voltage Input/Output (MVIO) support on 3 or 4 pins on Port C • 4 Configurable Custom Logic (CCL) cells, 6 Event System channels •
AVR EA-series • 8–64 KiB Flash • 28–48-pin package • internal 20 MHz oscillator • 24–32-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC) • Programmable Gain Amplifier (PGA) with up to 16x gain • 2 analog comparators • Three USARTs, one SPI, one dual-mode TWI • no Multi-Voltage Input/Output (MVIO) • 4 Configurable Custom Logic (CCL) cells, 6 Event System channels
XMEGA the ATxmega series offers a wide variety of peripherals and functionality such as: • Extended performance features, such as DMA, "Event System", and cryptography support • Extensive peripheral set with
ADCs Application-specific AVR • megaAVRs with special features not found on the other members of the AVR family, such as LCD controller,
USB controller, advanced PWM, CAN, etc.
FPSLIC (AVR with FPGA) •
FPGA 5k to 40k gates • SRAM for the AVR program code, unlike all other AVRs • AVR core can run at up to 50 MHz
32-bit AVRs • In 2006, Atmel released microcontrollers based on the 32-bit
AVR32 architecture. This was a completely different architecture unrelated to the 8-bit AVR, intended to compete with the
ARM-based processors. It had a 32-bit data path,
SIMD and
DSP instructions, along with other audio- and video-processing features. The instruction set was similar to other RISC cores, but it was not compatible with the original AVR (nor any of the various ARM cores). Since then support for AVR32 has been dropped from Linux as of kernel 4.12; compiler support for the architecture in
GCC was never mainlined into the compiler's central source-code repository and was available primarily in a vendor-supported fork. At the time that AVR32 was introduced, Atmel had already been a licensee of the
ARM architecture, with both
ARM7 and
ARM9 microcontrollers having been released prior to and concurrently with the AVR32; later Atmel focused most development effort on 32-bit chips with
ARM Cortex-M and
Cortex-A cores.
Device architecture package The AVRs have 32
single-byte registers and are classified as 8-bit RISC devices.
Flash,
EEPROM, and
SRAM are all integrated onto a single chip, removing the need for external memory in most applications. Some devices have a parallel external bus option to allow adding additional data memory or memory-mapped devices. Almost all devices (except the smallest TinyAVR chips) have serial interfaces, which can be used to connect larger serial EEPROMs or flash chips.
Program memory Program instructions are stored in
non-volatile flash memory. Although the
MCUs are 8-bit, each instruction takes one or two 16-bit words. The size of the program memory is usually indicated in the naming of the device itself (e.g., the ATmega64x line has 64 KB of flash, while the ATmega32x line has 32 KB). There is no provision for off-chip program memory; all code executed by the AVR core must reside in the on-chip flash. However, this limitation does not apply to the AT94 FPSLIC AVR/FPGA chips.
Internal data memory The data
address space consists of the
register file, I/O registers, and
SRAM. Some small models also map the program ROM into the data address space, but larger models do not.
Internal registers In the tinyAVR and megaAVR variants of the
AVR architecture, the working registers are mapped in as the first 32 data memory addresses (000016–001F16), followed by 64 I/O registers (002016–005F16). In devices with many peripherals, these registers are followed by 160 “extended I/O” registers, only accessible as
memory-mapped I/O (006016–00FF16). Actual SRAM starts after these register sections, at address 006016 or, in devices with "extended I/O", at 010016. Even though there are separate addressing schemes and optimized opcodes for accessing the register file and the first 64 I/O registers, all can also be addressed and manipulated as if they were in SRAM. The very smallest of the tinyAVR variants use a reduced architecture with only 16 registers (r0 through r15 are omitted) which are not addressable as memory locations. I/O memory begins at address 000016, followed by SRAM. In addition, these devices have slight deviations from the standard AVR instruction set. Most notably, the direct load/store instructions (LDS/STS) have been reduced from 2 words (32 bits) to 1 word (16 bits), limiting the total direct addressable memory (the sum of both I/O and SRAM) to 128 bytes. Conversely, the indirect load instruction's (LD) 16-bit address space is expanded to also include non-volatile memory such as Flash and configuration bits; therefore, the Load Program Memory (LPM) instruction is unnecessary and omitted. (For detailed info, see
Atmel AVR instruction set.) In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (000016–0FFF16). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space, which can be used optionally for mapping the internal EEPROM to the data address space (100016–1FFF16). The actual SRAM is located after these ranges, starting at 200016.
General-purpose input/output (GPIO) ports Each
GPIO port on a tiny or mega AVR drives up to eight pins and is controlled by three 8-bit registers: DDR
x, PORT
x and PIN
x, where
x is the port identifier. • DDR
x: Data Direction Register, configures the pins as either inputs or outputs. • PORT
x: Output port register. Sets the output value on pins configured as outputs. Enables or disables the
pull-up resistor on pins configured as inputs. • PIN
x: Input register, used to read an input signal. On some devices, this register can be used for pin toggling: writing a logic one to a PIN
x bit toggles the corresponding bit in PORT
x, irrespective of the setting of the DDR
x bit. Newer ATtiny AVRs, like ATtiny817 and its siblings, have their port control registers somewhat differently defined. xmegaAVR have additional registers for push/pull, totem-pole and pullup configurations.
EEPROM Almost all AVR microcontrollers have internal
EEPROM for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed. In most variants of the AVR architecture, this internal EEPROM memory is not mapped into the MCU's addressable memory space. It can only be accessed the same way an external peripheral device is, using special pointer registers and read/write instructions, which makes EEPROM access much slower than other internal RAM. However, some devices in the SecureAVR (AT90SC) family use a special EEPROM mapping to the data or program memory, depending on the configuration. The XMEGA family also allows the EEPROM to be mapped into the data address space. Since the number of writes to EEPROM is limited Atmel specifies 100,000 write cycles in their datasheets a well designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if the contents need to be changed.
Program execution Atmel's AVRs have a two-stage, single-level
pipeline design, meaning that the next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among
eight-bit microcontrollers. The AVR processors were designed with the efficient execution of
compiled C code in mind and have several built-in pointers for the task.
Instruction set The
AVR instruction set is more
orthogonal than those of most eight-bit microcontrollers, in particular the
8051 clones and
PIC microcontrollers with which AVR has competed. However, it is not completely regular: •
Pointer registers X, Y, and Z have addressing capabilities that are different from each other. •
Register locations R0 to R15 have more limited addressing capabilities than register locations R16 to R31. • I/O ports 0 to 31 can be bit addressed, unlike I/O ports 32 to 63. • CLR (clear all bits to zero) affects flags, while SER (set all bits to one) does not, even though they are complementary instructions. (CLR is pseudo-op for EOR R, R; while SER is short for LDI R,$FF. Arithmetic operations such as EOR modify flags, while moves/loads/stores/branches such as LDI do not.) • Accessing read-only data stored in the program memory (flash) requires special LPM instructions; the flash bus is otherwise reserved for instruction memory. Some chip-specific differences affect code generation. Code pointers (including return addresses on the stack) are two bytes long on chips with up to 128 KB of flash memory, but three bytes long on larger chips; not all chips have hardware multipliers; chips with over 8 KB of flash have branch and call instructions with longer ranges; and so forth. The mostly regular instruction set makes C (and even Ada) compilers fairly straightforward and efficient.
GCC has included AVR support for quite some time, and that support is widely used.
LLVM also has rudimentary AVR support. In fact, Atmel solicited input from major developers of compilers for small microcontrollers, to determine the instruction set features that were most useful in a compiler for high-level languages. The Arduino team borrowed from WinAVR for the Windows version of the
Arduino software. See
external links for sites relating to AVR development.
Features AVRs offer a wide range of features: • Multifunction, bi-directional general-purpose I/O ports with configurable, built-in
pull-up resistors • Multiple internal oscillators, including RC oscillator without external parts • Internal, self-programmable instruction
flash memory up to 256 KB (384 KB on XMega) •
In-system programmable using serial/parallel low-voltage proprietary interfaces or
JTAG • Optional boot code section with independent lock bits for protection • On-chip debugging (OCD) support through JTAG or
debugWIRE on most devices • The JTAG signals (TMS, TDI, TDO, and TCK) are multiplexed on
GPIOs. These pins can be configured to function as JTAG or GPIO depending on the setting of a
fuse bit, which can be programmed via
in-system programming (ISP) or HVSP. By default, AVRs with JTAG come with the JTAG interface enabled. •
debugWIRE uses the /RESET pin as a bi-directional communication channel to access on-chip debug circuitry. It is present on devices with lower pin counts, as it only requires one pin. • Internal data
EEPROM up to 4 KB • Internal
SRAM up to 16 KB (32 KB on XMega) • External 64 KB little endian data space on certain models, including the Mega8515 and Mega162. • The external data space is overlaid with the internal data space, such that the full 64 KB address space does not appear on the external bus and accesses to e.g. address 010016 will access internal RAM, not the external bus. • In certain members of the XMega series, the external data space has been enhanced to support both SRAM and SDRAM. As well, the data addressing modes have been expanded to allow up to 16 MB of data memory to be directly addressed. • 8-bit and 16-bit timers •
PWM output (some devices have an enhanced PWM peripheral which includes a dead-time generator) • Input capture that record a time stamp triggered by a signal edge • analog comparator • 10 or 12-bit
A/D converters, with multiplex of up to 16 channels • 12-bit
D/A converters • A variety of serial interfaces, including •
I²C compatible Two-Wire Interface (TWI) • Synchronous/asynchronous serial peripherals (
UART/USART) (used with
RS-232,
RS-485, and more) •
Serial Peripheral Interface Bus (SPI) • Universal Serial Interface (USI): a multi-purpose hardware communication module that can be used to implement an SPI, I2C or UART interface. •
Brownout detection •
Watchdog timer (WDT) • Multiple power-saving sleep modes • Lighting and motor control (
PWM-specific) controller models •
CAN controller support •
USB controller support • Proper full-speed (12 Mbit/s) hardware & Hub controller with embedded AVR. • Also freely available low-speed (1.5 Mbit/s) (
HID)
bitbanging software emulations •
Ethernet controller support •
LCD controller support • Low-voltage devices operating down to 1.8 V (to 0.7 V for parts with built-in DC–DC upconverter) • picoPower devices •
DMA controllers and "event system" peripheral communication. • Fast cryptography support for
AES and
DES == Programming interfaces ==