Below is the full
8086/
8088 instruction set of Intel (81 instructions total). These instructions are also available in 32-bit mode, in which they operate on 32-bit registers (
eax,
ebx, etc.) and values instead of their 16-bit (
ax,
bx, etc.) counterparts. The updated instruction set is grouped according to architecture (
i186,
i286,
i386,
i486,
i586/
i686) and is referred to as (32-bit)
x86 and (64-bit)
x86-64 (also known as
AMD64).
Original 8086/8088 instructions This is the original instruction set. In the 'Notes' column,
r means
register,
m means
memory address and
imm means
immediate (i.e. a value).
Added in specific processors ==== Added with
80186/
80188 ==== New instructions and instruction forms added in the Intel 80186 and 80188. Also present in the
NEC V20/V30 processors and their successors. ==== Added with
80286 ==== The new instructions added in 80286 add support for x86
protected mode. Some but not all of the instructions are available in
real mode as well. ==== Added with
80386 ==== The 80386 added support for 32-bit operation to the x86 instruction set. This was done by widening the general-purpose registers to 32 bits and introducing the concepts of
OperandSize and
AddressSize – most instruction forms that would previously take 16-bit data arguments were given the ability to take 32-bit arguments by setting their OperandSize to 32 bits, and instructions that could take 16-bit address arguments were given the ability to take 32-bit address arguments by setting their AddressSize to 32 bits. (Instruction forms that work on 8-bit data continue to be 8-bit regardless of OperandSize. Using a data size of 16 bits will cause only the bottom 16 bits of the 32-bit general-purpose registers to be modified – the top 16 bits are left unchanged.) The default OperandSize and AddressSize to use for each instruction is given by the D bit of the
segment descriptor of the current code segment - D=0 makes both 16-bit, D=1 makes both 32-bit. Additionally, they can be overridden on a per-instruction basis with two new instruction prefixes that were introduced in the 80386: • 66h: OperandSize override. Will change OperandSize from 16-bit to 32-bit if CS.D=0, or from 32-bit to 16-bit if CS.D=1. • 67h: AddressSize override. Will change AddressSize from 16-bit to 32-bit if CS.D=0, or from 32-bit to 16-bit if CS.D=1. The 80386 also introduced the two new segment registers FS and GS as well as the x86
control,
debug and
test registers. The new instructions introduced in the 80386 can broadly be subdivided into two classes: • Pre-existing opcodes that needed new mnemonics for their 32-bit OperandSize variants (e.g. CWDE, LODSD) • New opcodes that introduced new functionality (e.g. SHLD, SETcc) For instruction forms where the operand size can be inferred from the instruction's arguments (e.g. ADD EAX,EBX can be inferred to have a 32-bit OperandSize due to its use of EAX as an argument), new instruction mnemonics are not needed and not provided. ==== Added with
80486 ==== ==== Added in
P5/
P6-class processors ==== Integer/system instructions that were not present in the basic 80486 instruction set, but were added in various x86 processors prior to the introduction of SSE. (
Discontinued instructions are not included.)
Added as instruction set extensions ==== Added with
x86-64 ==== These instructions can only be encoded in 64 bit mode. They fall in four groups: • original instructions that reuse existing opcodes for a different purpose (MOVSXD replacing ARPL) • original instructions with new opcodes (SWAPGS) • existing instructions extended to a 64 bit address size (JRCXZ) • existing instructions extended to a 64 bit operand size (remaining instructions) Most instructions with a 64 bit operand size encode this using a
REX.W prefix; in the absence of the REX.W prefix, the corresponding instruction with 32 bit operand size is encoded. This mechanism also applies to most other instructions with 32 bit operand size. These are not listed here as they do not gain a new mnemonic in Intel syntax when used with a 64 bit operand size.
Bit manipulation extensions Bit manipulation instructions. For all of the
VEX-encoded instructions defined by BMI1 and BMI2, the operand size may be 32 or 64 bits, controlled by the VEX.W bit – none of these instructions are available in 16-bit variants. The VEX-encoded instructions are not available in Real Mode and Virtual-8086 mode - other than that, the bit manipulation instructions are available in all operating modes on supported CPUs.
Added with Intel TSX ==== Added with
Intel CET ==== Intel CET (Control-Flow Enforcement Technology) adds two distinct features to help protect against security exploits such as
return-oriented programming: a
shadow stack (CET_SS), and
indirect branch tracking (CET_IBT).
Added with XSAVE The XSAVE instruction set extensions are designed to save/restore CPU extended state (typically for the purpose of
context switching) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series of
state-components, each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. The EAX=0Dh
CPUID leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits.
Added with other cross-vendor extensions Added with other Intel-specific extensions Added with other AMD-specific extensions == x87 floating-point instructions ==