silicon integrated circuits welded to PCB in the Apollo guidance computer The AGC was designed at the
MIT Instrumentation Laboratory under
Charles Stark Draper, with hardware design led by
Eldon C. Hall. Early
architectural work came from
J. H. Laning Jr.,
Albert Hopkins,
Richard Battin, Ramon Alonso, The flight hardware was fabricated by
Raytheon, whose Herb Thaler was also on the architectural team. According to Kurinec et al., the chips were welded onto the boards rather than soldered as might be expected. Apollo Guidance Computer logic module drawings specify resistance-welding.
Logic hardware Following the use of
integrated circuit (IC) chips in the
Interplanetary Monitoring Platform (IMP) in 1963, IC technology was later adopted for the AGC. The Apollo flight computer was one of the first computers to use
silicon IC chips. While the Block I version used 4,100 ICs, each containing a single three-input
NOR gate, the later Block II version (used in the crewed flights) used about 2,800 ICs, mostly dual three-input NOR gates and smaller numbers of expanders and sense amplifiers.
Memory The computer had 2,048 words of erasable
magnetic-core memory and 36,864 words of
read-only core rope memory. Both had cycle times of 11.72 microseconds.) high-voltage
electroluminescent seven-segment display; these were driven by electromechanical
relays, limiting the update rate. Three five-digit signed numbers could also be displayed in
octal or
decimal, and were typically used to display
vectors such as space craft
attitude or a required velocity change (
delta-V). Although data was stored internally in
metric units, they were displayed as
United States customary units. This calculator-style interface was the first of its kind. The command module has two DSKYs connected to its AGC: one located on the main instrument panel and a second located in the lower equipment bay near a
sextant used for aligning the
inertial guidance platform. The lunar module had a single DSKY for its AGC. A
flight director attitude indicator (FDAI), controlled by the AGC, was located above the DSKY on the commander's console and on the LM.
Timing The AGC timing reference came from a 2.048 MHz
crystal clock. The clock was divided by two to produce a
four-phase 1.024 MHz clock which the AGC used to perform internal operations. The 1.024 MHz clock was also divided by two to produce a 512 kHz signal called the
master frequency; this signal was used to synchronize external Apollo spacecraft systems. The master frequency was further divided through a
scaler, first by five using a ring counter to produce a 102.4 kHz signal. This was then divided by two through 17 successive stages called F1 (51.2 kHz) through F17 (0.78125 Hz). The F10 stage (100 Hz) was fed back into the AGC to increment the
real-time clock and other involuntary counters using Pinc (discussed below). The F17 stage was used to intermittently run the AGC when it was operating in the
standby mode.
Central registers The AGC had four 16-bit
registers for general computational use, called the
central registers: •
A: The
accumulator, for general computation •
Z: The
program counter – the address of the next instruction to be executed •
Q: The remainder from the DV instruction, and the
return address after TC instructions •
L: The lower product after MP instructions There were also four locations in core memory, at addresses 20–23, dubbed
editing locations because whatever was stored there would emerge shifted or rotated by one bit position, except for one that shifted right seven bit positions, to extract one of the seven-bit interpretive op. codes that were packed two to a word. This was common to Block I and Block II AGCs.
Other registers . The AGC is opened up, showing its logic modules. The AGC had additional registers that were used internally in the course of operation: •
S: 12-bit memory address register, the lower portion of the memory address •
Bank/Fbank: 5-bit ROM bank register, to select the 1-
kiloword ROM bank when addressing in the fixed-switchable mode •
Ebank: 3-bit RAM bank register, to select the 256-word RAM bank when addressing in the erasable-switchable mode •
Sbank (super-bank): 1-bit extension to Fbank, required because the last 4 kilowords of the 36-kiloword ROM was not reachable using Fbank alone •
SQ: 4-bit sequence register; the current instruction •
G: 16-bit memory buffer register, to hold data words moving to and from memory •
X: The 'x' input to the
adder (the adder was used to perform all
1's complement arithmetic) or the increment to the program counter (
Z register) •
Y: The other ('y') input to the adder •
U: Not really a register, but the output of the adder (the
ones' complement sum of the contents of registers
X and
Y) •
B: General-purpose buffer register, also used to pre-fetch the next instruction. At the start of the next instruction, the upper bits of
B (containing the next op. code) were copied to
SQ, and the lower bits (the address) were copied to
S. •
C: Not a separate register, but the ones' complement of the
B register •
IN: Four 16-bit input registers •
OUT: Five 16-bit output registers
Instruction set The
instruction format used 3 bits for
opcode, and 12 bits for address. Block I had 11 instructions: TC, CCS, INDEX, XCH, CS, TS, AD, and MASK (basic), and SU, MP, and DV (extra). The first eight, called
basic instructions, were directly accessed by the 3-bit op. code. The final three were denoted as
extracode instructions because they were accessed by performing a special type of TC instruction (called EXTEND) immediately before the instruction. The Block I AGC instructions consisted of the following: ;TC (transfer control): An unconditional branch to the address specified by the instruction. The return address was automatically stored in the Q register, so the TC instruction could be used for subroutine calls. ;CCS (count, compare, and skip): A complex conditional branch instruction. The A register was loaded with data retrieved from the address specified by the instruction. (Because the AGC uses
ones' complement notation, there are two representations of zero. When all bits are set to zero, this is called
plus zero. If all bits are set to one, this is called
minus zero.) The
diminished absolute value (DABS) of the data was then computed and stored in the A register. If the number was greater than zero, the DABS decrements the value by 1; if the number was negative, it is complemented before the decrement is applied—this is the absolute value.
Diminished means "decremented but not below zero". Therefore, when the AGC performs the DABS function, positive numbers will head toward plus zero, and so will negative numbers but first revealing their negativity via the four-way skip below. The final step in CCS is a four-way skip, depending upon the data in register A before the DABS. If register A was greater than 0, CCS skips to the first instruction immediately after CCS. If register A contained plus zero, CCS skips to the second instruction after CCS. Less than zero causes a skip to the third instruction after CCS, and minus zero skips to the fourth instruction after CCS. The primary purpose of the count was to allow an ordinary loop, controlled by a positive counter, to end in a CCS and a TC to the beginning of the loop, equivalent to an
IBM 360's BCT. The absolute value function was deemed important enough to be built into this instruction; when used for only this purpose, the sequence after the CCS was TC *+2, TC *+2, AD ONE. A curious side effect was the creation and use of
CCS-holes when the value being tested was known to be never positive, which occurred more often than one might suppose. That left two whole words unoccupied, and a special committee was responsible for assigning data constants to these holes. ;INDEX: Add the data retrieved at the address specified by the instruction to the next instruction. INDEX can be used to add or subtract an index value to the
base address specified by the operand of the instruction that follows INDEX. This method is used to implement arrays and table look-ups; since the addition was done on both whole words, it was also used to modify the op. code in a following (extracode) instruction, and on rare occasions both functions at once. ;RESUME: A special instance of INDEX (INDEX 25). This is the instruction used to return from interrupts. It causes execution to resume at the interrupted location. ;XCH (exchange): Exchange the contents of memory with the contents of the A register. If the specified memory address is in fixed (read-only) memory, the memory contents are not affected, and this instruction simply loads register A. If it is in erasable memory, overflow "correction" is achieved by storing the leftmost of the 16 bits in A as the sign bit in memory, but there is no exceptional behavior like that of TS. ;CS (clear and subtract): Load register A with the ones' complement of the data referenced by the specified memory address. ;TS (transfer to storage): Store register A at the specified memory address. TS also detects, and corrects for,
overflows in such a way as to propagate a carry for multi-precision add/subtract. If the result has no overflow (leftmost 2 bits of A the same), nothing special happens; if there is overflow (those 2 bits differ), the leftmost one goes the memory as the sign bit, register A is changed to +1 or −1 accordingly, and control skips to the second instruction following the TS. Whenever overflow is a possible but abnormal event, the TS was followed by a TC to the no-overflow logic; when it is a normal possibility (as in multi-precision add/subtract), the TS is followed by CAF ZERO (CAF = XCH to fixed memory) to complete the formation of the carry (+1, 0, or −1) into the next higher-precision word. Angles were kept in single precision, distances and velocities in double precision, and elapsed time in triple precision. ;AD (add): Add the contents of memory to register A and store the result in A. The 2 leftmost bits of A may be different (overflow state) before and/or after the AD. The fact that overflow is a state rather than an event forgives limited extents of overflow when adding more than two numbers, as long as none of the intermediate totals exceed twice the capacity of a word. ;MASK: Perform a bit-wise (boolean)
and of memory with register A and store the result in register A. ;MP (multiply): Multiply the contents of register A by the data at the referenced memory address and store the high-order product in register A and the low-order product in register LP. The parts of the product agree in sign. ;DV (divide): Divide the contents of register A by the data at the referenced memory address. Store the quotient in register A and the absolute value of the remainder in register Q. Unlike modern machines,
fixed-point numbers were treated as fractions (notional decimal point just to right of the sign bit), so you could produce garbage if the divisor was not larger than the dividend; there was no protection against that situation. In the Block II AGC, a double-precision dividend started in A and L (the Block II LP), and the correctly signed remainder was delivered in L. That considerably simplified the subroutine for double precision division. ;SU (subtract): Subtract (ones' complement) the data at the referenced memory address from the contents of register A and store the result in A. Instructions were implemented in groups of 12 steps, called
timing pulses. The timing pulses were named TP1 through TP12. Each set of 12 timing pulses was called an instruction
subsequence. Simple instructions, such as TC, executed in a single subsequence of 12 pulses. More complex instructions required several subsequences. The multiply instruction (MP) used 8 subsequences: an initial one called MP0, followed by an MP1 subsequence which was repeated 6 times, and then terminated by an MP3 subsequence. This was reduced to 3 subsequences in Block II. Each timing pulse in a subsequence could trigger up to 5
control pulses. The control pulses were the signals which did the actual work of the instruction, such as reading the contents of a register onto the bus, or writing data from the bus into a register.
Memory (ROM) Block I AGC memory was organized into 1 kiloword banks. The lowest bank (bank 0) was erasable memory (RAM). All banks above bank 0 were fixed memory (ROM). Each AGC instruction had a 12-bit address field. The lower bits (1–10) addressed the memory inside each bank. Bits 11 and 12 selected the bank: 00 selected the erasable memory bank; 01 selected the lowest bank (bank 1) of fixed memory; 10 selected the next one (bank 2); and 11 selected the
Bank register that could be used to select any bank above 2. Banks 1 and 2 were called
fixed-fixed memory, because they were always available, regardless of the contents of the Bank register. Banks 3 and above were called
fixed-switchable because the selected bank was determined by the bank register. The Block I AGC initially had 12 kilowords of fixed memory, but this was later increased to 24 kilowords. Block II had 36 kilowords of fixed memory and 2 kilowords of erasable memory. The AGC transferred data to and from memory through the G register in a process called the
memory cycle. The memory cycle took 12 timing pulses (11.72 μs). The cycle began at timing pulse 1 (TP1) when the AGC loaded the memory address to be fetched into the S register. The memory hardware retrieved the data word from memory at the address specified by the S register. Words from erasable memory were deposited into the G register by timing pulse 6 (TP6); words from fixed memory were available by timing pulse 7. The retrieved memory word was then available in the G register for AGC access during timing pulses 7 through 10. After timing pulse 10, the data in the G register was written back to memory. The AGC memory cycle occurred continuously during AGC operation. Instructions needing memory data had to access it during timing pulses 7–10. If the AGC changed the memory word in the G register, the changed word was written back to memory after timing pulse 10. In this way, data words cycled continuously from memory to the G register and then back again to memory. The lower 15 bits of each memory word held AGC instructions or data, with each word being protected by a 16th odd parity bit. This bit was set to 1 or 0 by a parity generator circuit so a count of the 1s in each memory word would always produce an odd number. A parity checking circuit tested the parity bit during each memory cycle; if the bit didn't match the expected value, the memory word was assumed to be corrupted and a
parity alarm panel light was illuminated.
Interrupts and involuntary counters The AGC had five vectored
interrupts: •
Dsrupt was triggered at regular intervals to update the user display (DSKY). •
Erupt was generated by various hardware failures or alarms. •
Keyrupt signaled a key press from the user's keyboard. •
T3Rrupt was generated at regular intervals from a hardware timer to update the AGC's
real-time clock. •
Uprupt was generated each time a 16-bit word of uplink data was loaded into the AGC. The AGC responded to each interrupt by temporarily suspending the current program, executing a short interrupt service routine, and then resuming the interrupted program. The AGC also had 20 involuntary
counters. These were memory locations which functioned as up/down counters, or shift registers. The counters would increment, decrement, or shift in response to internal inputs. The increment (
Pinc), decrement (
Minc), or shift (
Shinc) was handled by one subsequence of microinstructions inserted between any two regular instructions. Interrupts could be triggered when the counters overflowed. The T3rupt and Dsrupt interrupts were produced when their counters, driven by a 100 Hz hardware clock, overflowed after executing many Pinc subsequences. The Uprupt interrupt was triggered after its counter, executing the Shinc subsequence, had shifted 16 bits of uplink data into the AGC.
Standby mode The AGC had a power-saving mode controlled by a
standby allowed switch. This mode turned off the AGC power, except for the 2.048 MHz clock and the scaler. The F17 signal from the scaler turned the AGC power and the AGC back on at 1.28 second intervals. In this mode, the AGC performed essential functions, checked the standby allowed switch, and, if still enabled, turned off the power and went back to sleep until the next F17 signal. In the standby mode, the AGC slept most of the time; therefore it was not awake to perform the Pinc instruction needed to update the AGC's real time clock at 10 ms intervals. To compensate, one of the functions performed by the AGC each time it awoke in the standby mode was to update the real time clock by 1.28 seconds. The standby mode was designed to reduce power by 5 to 10 W (from 70 W) during midcourse flight when the AGC was not needed. However, in practice, the AGC was left on during all phases of the mission and this feature was never used.
Data buses The AGC had a 16-bit read bus and a 16-bit write bus. Data from central registers (A, Q, Z, or LP), or other internal registers could be gated onto the read bus with a control signal. The read bus connected to the write bus through a non-inverting buffer, so any data appearing on the read bus also appeared on the write bus. Other control signals could copy write bus data back into the registers. Data transfers worked like this: To move the address of the next instruction from the B register to the S register, an RB (read B) control signal was issued; this caused the address to move from register B to the read bus, and then to the write bus. A WS (write S) control signal moved the address from the write bus into the S register. Several registers could be read onto the read bus simultaneously. When this occurred, data from each register was inclusive-
ORed onto the bus. This inclusive-
OR feature was used to implement the Mask instruction, which was a logical
AND operation. Because the AGC had no native ability to do a logical
AND, but could do a logical
OR through the bus and could complement (invert) data through the C register,
De Morgan's theorem was used to implement the equivalent of a logical
AND. This was accomplished by inverting both operands, performing a logical
OR through the bus, and then inverting the result.
Software standing next to listings of the software she and her MIT team produced for the
Apollo Project. AGC software was written in AGC
assembly language and stored on
rope memory. The bulk of the software was on read-only rope memory and thus could not be changed in operation, but some key parts of the software were stored in standard read-write
magnetic-core memory and could be overwritten by the astronauts using the DSKY interface, as was done on
Apollo 14. A simple
real-time operating system designed by
J. Halcombe Laning consisting of the 'Exec', a batch job-scheduling using
cooperative multi-tasking, and an
interrupt-driven
pre-emptive scheduler called the 'Waitlist' which scheduled timer-driven 'tasks', controlled the computer. Tasks were short threads of execution which could reschedule themselves for re-execution on the Waitlist, or could kick off a longer operation by starting a 'job' with the Exec. Calculations were carried out using the
metric system, but display readouts were in units of feet, feet per second, and nautical miles – units that the Apollo astronauts were accustomed to. When the design requirements for the AGC were defined, necessary software and programming techniques did not exist so they had to be designed from scratch. Many of the trajectory and guidance algorithms used were based on earlier work by
Richard Battin. on the lunar module led by George Cherry. Details of these programs were implemented by a team under the direction of
Margaret Hamilton. Hamilton was very interested in how the astronauts would interact with the software and predicted the types of errors that could occur due to human error. The Apollo Guidance computer has been called "The fourth astronaut" for its role in helping the three astronauts who relied on it:
Neil Armstrong,
Buzz Aldrin and
Michael Collins. ==Block II==