Cycle stealing

Some processors were designed to allow cycle stealing, or at least supported it easily. This was the case for the Motorola 6800 and MOS 6502 systems due to a design feature which meant the CPU only accessed memory every other clock cycle. Using RAM that was running twice as fast as the CPU clock allowed a second system to interleave its accesses between the CPUs by timing themselves on every other clock cycle. This was widely used for updating the display using main memory as a framebuffer. Common RAM of the late 1970s ran at 2 MHz, so most machines had a CPU running around 1 MHz. The BBC Micro secured a supply of 4 MHz RAM which allowed its CPU to run at 2 MHz. Another common solution was to use separate banks of memory that stored instructions vs. data, or more than one pool of data. In these cases the I/O systems can access their data memory while the processor is using a different bank. One example is the Zilog Z80, whose M1 line indicates that the processor is reading instructions; if those instructions are in a different bank, or more commonly ROM, the I/O systems can access RAM without interfering with the processor. ==Modern architecture==

Cycle stealing is difficult to achieve in modern systems due to many factors such as pipelining, where pre-fetch and concurrent elements are constantly accessing memory, leaving few predictable idle times to sneak in memory access. DMA is the only formal and predictable method for external devices to access RAM. This term is less common in modern computer architecture (above 66-100 MHz), where the various external buses and controllers generally run at different rates, and CPU internal operations are no longer closely coupled to I/O bus operations. ==Examples in actual computer systems==

Unexpected cycle stealing by the rendezvous radar during descent nearly caused the Apollo 11 landing to be aborted, but the design of the Guidance Computer allowed the landing to continue by dropping low-priority tasks. The IBM 1130's "cycle steal" is really DMA because the CPU clock is stopped during memory access. Several I/O controllers access RAM this way. They self-arbitrate via a fixed priority scheme. Most controllers deliberately pace RAM access to minimize impact on the system's ability to run instructions, but others, such as graphic video adapters, operate at higher speed and may slow down the system. The cycle-stealing concept of the 1130 permits the CPU program to start an operation on an I/O device and then continue the mainline program while the I/O device is performing its operation. Each I/O device that operates in this manner takes (steals) a cycle from the CPU when it is needed. The CPU is "tied up" only one cycle while a data character is being transferred. The frequency at which devices steal cycles depends on the type of device. Since the CPU is much faster than any I/O device on the system, the CPU may be performing another function, such as arithmetic, at the same time an I/O operation is being performed. In fact, several I/O operations may be overlapped with each other and with other CPU functions. Cycle stealing has been the cause of major performance degradation on machine such as the Sinclair QL, where, for economy reasons, the video RAM was not dual access. Consequently, the M68008 CPU was denied access to the memory bus when the ZX8301 "master controller" was accessing memory, and the machine performed poorly when compared with machines using similar processors at similar speeds. ==References==