Cyrix 5x86

The Cyrix 5x86 processor, codename "M1sc", was based on a scaled-down version of the "M1" core used in the Cyrix 6x86, which provided 80% of the performance for a 50% decrease in transistors over the 6x86 design. It had the 32-bit memory bus of an ordinary 486 processor, but internally had much more in common with fifth-generation processors such as the Cyrix 6x86, the AMD K5, and the Intel Pentium, and even the sixth-generation Intel Pentium Pro. The chip featured near-complete support for i486 instructions, but very limited support for Pentium instructions. Some performance-enhancing features of the CPU were intentionally disabled due to potentially stability-threatening bugs which were not fixed before release time (these features can be enabled with freely downloadable software utilities; see below). The similarly named SGS-Thomson (STMicroelectronics) ST5x86 and IBM 5x86C were licensed rebrandings of the Cyrix design (IBM and ST physically produced Cyrix's CPUs for them), marketed separately but identical for practical purposes, apart from the availability of a 75 MHz edition which Cyrix did not bring to market, and slight differences in voltage requirements. The Cyrix 5x86 design, however, should not be confused with the similarly named AMD Am5x86 which was essentially a clock-quadrupled 486 (not an all-new design like the Cyrix part) but which had broadly similar performance, used the same Socket 3, and was introduced at the end of the same year. Cyrix's 5x86 was a very short-lived chip, having a market life of only six months. It is likely Cyrix could have continued to successfully sell processors based on Socket 3, but canned the 5x86 so that it would not compete with its then new 6x86 offerings. ==Controversies and anomalies==

The official Cyrix 5x86 website boasted about several features of the chip that were disabled by default in the final versions. The most controversial of these features was the branch prediction feature, which was enabled in the benchmarks results on the company website when comparing the chip to Intel's Pentium processor. While it was possible to enable the extra features using a special software utility, it usually resulted in an unstable system, especially on earlier steppings of the chip when running 32-bit code. There are also many rumours surrounding a 133 MHz, clock-quadrupled version of the Cyrix 5x86. The 133 MHz version is very rare, however, and producers of upgrade kits were given preferential access to it, notably Gainbery. Some of the 100 and 120 MHz parts also contain support for the 4X multiplier setting, and some of these chips may also work at 133 MHz. However, the 5x86 is not known to overclock well; 120 MHz is generally considered to be pushing the limitations of the process on which it was fabricated. An 80 MHz (2×40 MHz) 5x86 also exists, but is unclear as to whether or not it was ever officially released. IBM's 5x86C was considered to be more conservatively rated than the Cyrix branded parts, and operated at a lower voltage (3.3V). For example: what Cyrix would rate as a 100 MHz part, IBM would mark as 75 MHz. IBM 5x86C was available as 75 MHz and 100 MHz parts. A few examples of 120 MHz parts also exist, but they have early production dates indicating that they may have been produced prior to IBM's decision to scale back clock speeds. 5x86C also had a much longer production run than the Cyrix branded parts. IBM continued to produce 5x86C at least until late 1998 (QFP only), whereas Cyrix's own part was discontinued in 1996. Parts which implement the 4X multiplier or Stepping 1 Rev 3 cores are not known to exist. ==Specifications==

• iDX4WB pinout, 168 pins • Socket 3 • 2.0 million transistors on 0.65 micrometre process • 144 mm2 die • 3.45 volts • 16 kilobytes unified level-one cache 100 MHz capable edition for 33 MHz (33×3), and 50 MHz (50×2) front side bus 100 MHz capable edition for 33 MHz (33×3), and 25 MHz (25×4) front side bus 120/133 MHz capable edition for 40 MHz (40×3) and 33 MHz (33×4) front side bus. ==References==