Cyrix III

The Cyrix III was launched in late February 2000. It was initially based on the Joshua core, and was available in two performance ratings of 500 and 533 MHz, with the PR500 being $84 per unit and the PR533 $99. National Semiconductor would be the producer of the chips. 650 and 667 MHz versions of the Cyrix III were available starting January 2001. The 650 MHz version would cost $55 per chip while the 667 would be $60 and both were based on the Samuel core. The 700 MHz version of the Cyrix III was available on January 19, 2001. The price would be $62 per chip in bulk quantities. This was the last III chip released using the Samuel core, as the Samuel II was expected to be released in March. Just a month later in February 2001, Cyrix III chips based on the Samuel 2 core were announced. An initial 750 MHz version would be available, with 800 and 850 MHz coming later. The chips would have a 100 and 133 MHz FSB, 128 KB of L1 cache along with MMX and 3DNow instructions. The chips would be produced using a 0.15 micron process and have a die size of 52 square mm. VIA planned to release a later version of the chip, code-named Ezra/C5C with a 0.13 micron process and speeds of 750 MHz up to possibly 1 GHz. == CPU cores ==

Joshua The pre-release Cyrix III CPUs were based upon a 22 million transistor Joshua core designed by Cyrix. This CPU core was a typical Cyrix design: superscalar with speculative execution and a high IPC rate but rather low clock rates. To emphasize the higher performance of their designs compared to the competitors' offerings, Cyrix used a system with a "P-Rating" higher than the clock rate. The floating point unit of the processor had supposedly been updated from the lacklustre unit in the 6x86/MII series. When the chip reached reviewers, the weighted integer/floating-point performance was found to be fairly low compared to the competition. Samuel Because the Joshua core was such a mixed result in thermal output, core size, and performance, VIA switched almost immediately to an 11 million transistor Samuel core designed by Centaur Technology. The Samuel core was a simpler design, being an evolution of the WinChip processors (the unreleased WinChip 4). Samuel was designed for higher clock speeds, with more L1 cache (but no L2), and used smaller manufacturing technology. While this version of Cyrix III still had sub-par performance compared to the competition from Intel and AMD, it was quite power efficient and consisted of only half the number of transistors of Cyrix's creation. VIA dropped the criticized P-Rating with new processors based on the Samuel core, in favor of simply distinguishing them by their actual clock speed. Samuel 2 The Samuel 2 core is a revision to the Samuel core. The Centaur Technology team added an on-die 64 KiB L2 cache and moved to a 150 nm manufacturing process. These changes improved per-clock performance, reduced power demands, and increased clock speed scalability. == Models & variants ==

The Cyrix III was later renamed C3, as it was not built upon Cyrix technology at all. == See also ==