In the context of semi-custom digital design, pre-characterized digital information is often abstracted in the form of the above-mentioned 2-D look-up table (LUT). The idea behind the semi-custom design method is to use blocks of pre-built and tested components to build something larger, say, a chip. In this context, the blocks are
logic gates such as NAND, OR, AND, etc. Although, in reality, these gates will be composed of transistors, a semi-custom engineer will only be aware of the delay information from the input pin to the output pin, called a timing arc. The 2D table represents the variability of the gate's delay concerning the two independent variables, usually the rate of change of the signal at the input and the load at the output pin. These two variables are called slew and load in design parlance. A
static timing analysis engine will first calculate the delay of the individual cells and string them together to do further analysis. == Statistical delay calculation ==