Domino logic

Dynamic logic differs from static logic by including a clock signal to speed up performance. In CMOS dynamic logic gates, the gate output is precharged to the power supply voltage while the clock is off (the "precharge" phase), and then is evaluated to the correct logic state while the clock is on (the "evaluation" phase) by draining the relevant NMOS transistors in the pull-down network. ==Domino logic operation==

In order to cascade dynamic logic gates, one solution is domino logic, which inserts an ordinary static inverter between stages. In a multistage domino logic cascade structure, the evaluation of each stage ripples the next stage for evaluation, similar to dominoes falling one after the other. Once evaluated, the node states cannot return to "1" until the next precharge phase begins. ==Modifications to domino logic==

Charge sharing can cause difficulties for domino logic signal integrity; during the evaluation phase, NMOS transistors next to the output which are on may cause undesired discharging from the output node. To fix this, a keeper transistor can be used. This keeper transistor is a PMOS transistor with its gate connected to the inverter output, its source connected to the power supply, and its drain connected to the inverter input. The keeper transistor thus connects the dynamic node to the power supply whenever it is supposed to be in the "1" state, allowing the output to be correctly restored despite the charge sharing. Another issue in domino logic is its noninverting property; that is, it can only implement gates that do not have inversions at their outputs (such as AND gates and OR gates, as opposed to NAND gates and NOR gates). To rectify this property, some variants of domino logic are differential or dual-rail in nature, using inverted and non-inverted inputs to implement the logic function and its inverse. These varieties also include cross-coupled pFETs to attenuate noise. ==See also==