To provide even more modularity with reduced cost,
memory and
I/O buses (and the required
control and
power buses) were sometimes combined into a single unified system bus. Modularity and cost became important as computers became small enough to fit in a single cabinet (and customers expected similar price reductions).
Digital Equipment Corporation (DEC) further reduced cost for mass-produced
minicomputers, and
memory-mapped I/O into the memory bus, so that the devices appeared to be memory locations. This was implemented in the
Unibus of the
PDP-11 around 1969, eliminating the need for a separate I/O bus. Even computers such as the
PDP-8 without memory-mapped I/O were soon implemented with a system bus, which allowed modules to be plugged into any slot. Some authors called this a new streamlined "model" of computer architecture. Many early microcomputers (with a CPU generally on a single
integrated circuit) were built with a single system bus, starting with the
S-100 bus in the
Altair 8800 computer system in about 1975. The
IBM PC used the
Industry Standard Architecture (ISA) bus as its system bus in 1981. The passive backplanes of early models were replaced with the standard of putting the CPU and RAM on a
motherboard, with only optional
daughterboards or
expansion cards in system bus slots. using a system bus The
Multibus became a standard of the
Institute of Electrical and Electronics Engineers as IEEE standard 796 in 1983.
Sun Microsystems developed the
SBus in 1989 to support smaller expansion cards. The easiest way to implement
symmetric multiprocessing was to plug in more than one CPU into the shared system bus, which was used through the 1980s. However, the shared bus quickly became the bottleneck and more sophisticated connection techniques were explored. Even in very simple systems, at various times the data bus is driven by the program memory, by RAM, and by I/O devices. To prevent
bus contention on the data bus, at any one instant only one device drives the data bus. In very simple systems, only the data bus is required to be a bidirectional bus. In very simple systems, the
memory address register always drives the address bus, the
control unit always drives the control bus, and an
address decoder selects which particular device is allowed to drive the data bus during this bus cycle. In very simple systems, every
instruction cycle starts with a READ memory cycle where program memory drives the instruction onto the data bus while the
instruction register latches that instruction from the data bus. Some instructions continue with a WRITE memory cycle where the
memory data register drives data onto the data bus into the chosen RAM or I/O device. Other instructions continue with another READ memory cycle where the chosen RAM, program memory, or I/O device drives data onto the data bus while the memory data register latches that data from the data bus. More complex systems have a
multi-master bus—not only do they have many devices that each drive the data bus, but also have many
bus masters that each drive the address bus. The address bus as well as the data bus in
bus snooping systems is required to be a bidirectional bus, often implemented as a
three-state bus. To prevent bus contention on the address bus, a
bus arbiter selects which particular bus master is allowed to drive the address bus during this bus cycle. ==Dual Independent Bus==