Electronic system-level design and verification

Whether ESL or other systems, design refers to "the concurrent design of the hardware and software parts of an electronic product." == Tools ==

There are various types of EDA tool used for ESL design. The key component is the Virtual Platform which is essentially a simulator. The Virtual Platform most commonly supports Transaction-level modeling (TLM), where operations of one component on another are modelled with a simple method call between the objects modelling each component. This abstraction gives a considerable speed up over cycle-accurate modelling, since thousands of net-level events in the real system can be represented by simply passing a pointer, e.g. to model that an Ethernet packet has been received, SystemC is often used. Other tools support import and export or intercommunication with components modelled at other levels of abstraction. For instance, an RTL component be converted into a SystemC model using VtoC or Verilator. And High Level Synthesis can be used to convert C models of a component into an RTL implementation. == Verification ==

In ESL design and verification, verification testing is used to prove the integrity of the design of the system or device. Numerous verification techniques may be applied; these test methods are usually modified or customized to better accommodate the system or device under test. Common ESL verification methods include, but are not limited to: • Modular architecture • Constrained random stimulus generation • Error injection • Complete simulation environments Verification is often provided by the system/device designer, but in many instances, additional independent verification is required == Challenges and criticism ==

Some criticisms of ESL design and verification have been raised. These include too much focus on C-based languages and challenges in representing parallel processes. It can also be argued that ESL design and verification is a subset of verification and validation. == See also ==