Elmore delay

A simple interconnect (wire) between two components can be modeled as an RC ladder network. If the wire is divided into ‘N’ segments, each consisting of resistance ‘R’ and capacitance ‘C’, the resulting circuit is of order N. Using a first-order Padé approximation, the complex circuit can be reduced to a single equivalent resistance R_{\text{eq}} and capacitance C_{\text{eq}}. The time constant of this first-order system is R_{\text{eq}} * C_{\text{eq}}, which represents Elmore delay. == Calculating Elmore delay ==

Consider a simple wire connecting two nodes namely A and B as shown in Fig.1., the Elmore delay (T_{D}) from A to B is calculated as follows. T_D = R_1 C_1 + (R_1 + R_2) C_2 + (R_1 + R_2 + R_3) C_3 + (R_1 + R_2 + R_3 + R_4) (C_4 + C_{Inp_{B}}) More generally, for a interconnect modelled with 'n' series RC network, the Elmore Delay (T_{D}) is given by \sum_{i=1}^n \left( \sum_{j=1}^i R_j \right) C_i and the 50% output propagation delay is given by \ln(2) \cdot T_D . == Types of Elmore delay ==

Elmore delay is commonly divided into two components for simplicity: intrinsic and extrinsic Elmore delay. Intrinsic Elmore delay arises from the parasitic resistance and capacitance of the interconnect itself, while extrinsic Elmore delay is attributed to the loading network, typically modeled as the input capacitance of loading network at node B (denoted as CInp_B). Intrinsic and Extrinsic Elmore delay denoted by T_{\text{Intrinsic}} and T_{\text{Extrinsic}} of the RC network in Fig.1. are given as follows, T_{\text{Intrinsic}} = R_1 C_1 + (R_1 + R_2) C_2 + (R_1 + R_2 + R_3) C_3 + (R_1 + R_2 + R_3 + R_4) C_4 T_{\text{Extrinsic}} = (R_1 + R_2 + R_3 + R_4) C_{Inp_{B}} Therefore total Elmore delay: T_D = T_{\text{Intrinsic}} + T_{\text{Extrinsic}} == Elmore delay of branching RC networks ==

To calculate the Elmore delay of a branching RC network, the capacitances on branches that do not lie along the signal path to the output are lumped at the corresponding branch points on the main path. The Elmore delay is then computed as if it were a simplified RC network. In Fig. 2, to calculate the Elmore delay from node A to node B, the resistances R_5, R_6 , and R_7 in the branching network are ignored. However, the capacitances C_5, C_6 , and C_7 in the branching path C are lumped at the branching node on the main signal path, effectively placed in parallel with capacitance C_2. This simplification allows the Elmore delay to be calculated using the simplified RC network. Therefore, Elmore Delay from A to B denoted by T_{D_{A-B}} is as follows,T_{D_{A-B}} = R_1 C_1 + (R_1 + R_2)(C_2 + C_5 + C_6 + C_7) + (R_1 + R_2 + R_3) C_3 + (R_1 + R_2 + R_3 + R_4) C_4 Similarly, to calculate the Elmore Delay from A to C, the resistances R_3 and R_4 are ignored and capacitance C_3 and C_4 are lumped into the branching node, and we simply find the delay of simple RC network from A to C. Elmore Delay from node A to C (T_{D_{A-C}}) is given by, T_{D_{A-C}} = R_1 C_1 + (R_1 + R_2)(C_2 + C_3 + C_4) + (R_1 + R_2 + R_5) C_5 + (R_1 + R_2 + R_5 + R_6) C_6 + (R_1 + R_2 + R_5 + R_6 + R_7) C_7 and the 50% output propagation delay is given by \ln(2) \cdot T_{D_{A-C}} . == Techniques to reduce Elmore delay ==

A straightforward method to reduce (intrinsic) Elmore delay is to insert buffers along long interconnects. This breaks the RC network into smaller segments, thereby lowering the overall delay. From the above equations, it is clear that the Elmore delay between two logic gates connected by a simple wire is mainly caused by the parasitic resistance of the wire. The resistance R of a wire is given by R = \rho \frac{L}{A} where ρ is the resistivity, L is the wire length, and A is the cross-sectional area. Since resistance is inversely proportional to the cross-sectional area, increasing A reduces the resistance. However, increasing the cross-sectional area also increases the capacitance, given by C = \frac{\varepsilon_0 A}{d} where ε0 is the permittivity and d is the separation distance. To effectively reduce Elmore delay, the wire geometry can be optimized as shown in Fig.3.. A commonly used technique is wire tapering, where the wire’s cross-sectional area is larger near the driver and tapers down towards the load. This design balances the trade-off between resistance and capacitance, minimizing their combined effect and reducing overall delay more efficiently. == Limitations of delay optimization techniques ==

With shrinking semiconductor technology nodes, the number of metal layers available for routing increases. However, routing signals from the upper metal layers down to the silicon to insert buffers requires multiple vias. These vias consume valuable routing resources, introduce additional parasitics along the path, and can block other signal routes, leading to congestion. Similarly, wire tapering can cause routing congestion and poor track utilization because the varying cross-sectional area reduces available routing space. This non-uniformity makes it difficult to route other wires in the remaining spacing. Additionally, for interconnects related to power delivery, the thinner wire sections introduced by tapering increase the risk of electromigration, which may lead to physical wire damage and long-term reliability issues. == See also ==