The eZ80 has a three-stage pipeline: fetch, decode, and execute. When an instruction changes the
program counter, it flushes the instructions that the CPU is currently processing. Available at up to 50 MHz (2004), the performance is comparable to a Z80 clocked at 150 MHz if fast memory is used (i.e. no wait states for
opcode fetches, for data, or for I/O) or even higher in some applications (a 16-bit addition is 11 times as fast as in the original). The original Z80-compatible 16-bit register configuration is supported. The eZ80 also supports direct continuous addressing of 16
MB of memory without a
memory management unit, by extending most registers (HL, BC, DE, IX, IY, SP, and PC) from 16 to 24 bits. In order to do so, the CPU has a full 24-bit address mode called ADL mode. In ADL mode, all Z80 16-bit registers are extended to 24 bits with additional upper 8-bit registers. For example, the HL register pair is extended with an uppermost register called HLU. The resulting 24-bit multi-byte register is collectively accessed by its old name, HL. The upper registers cannot be accessed individually. Although the eZ80 handles 24-bit math and moves, it only supports 8-bit operations for logic functions such as AND, OR, and XOR. The processor has a 24-bit
arithmetic unit and overlapped processing of several instructions (the three-stage pipeline) which are the two primary reasons for its speed. Unlike the older
Z280 and
Z380 it does not have (or need) a cache memory. Instead, it is intended to work with fast
SRAM directly as main memory (as this had become much cheaper). Nor does it have the multiplexed bus of the Z280, making it as easy to work with (interface to) as the original Z80 and Z180, and equally predictable when it comes to exact execution times. The chip has a
memory interface that is similar to the original Z80, including the bus request/acknowledge pins, and adds four integrated chip selects. Versions are available with on-chip flash memory and on-chip zero wait-state SRAM (up to 256
KB flash memory and 16 KB SRAM) but there are also external buses on all models. == Variants ==