Flip-flops and latches can be divided into common types: SR (set-reset), D (data), T (toggle), and JK (see History section above). The behavior of a particular type can be described by the characteristic equation that derives the
next output () in terms of the input signal(s) and/or the current output, Q.
Asynchronous set-reset latches When using static gates as building blocks, the most fundamental latch is the asynchronous
set-reset (SR) latch. Its two inputs S and R can set the internal state to 1 using the combination S=1 and R=0, and can reset the internal state to 0 using the combination S=0 and R=1. The SR latch can be constructed from a pair of cross-coupled
NOR or
NAND logic gates. The stored bit is present on the output marked Q. It is convenient to think of NAND, NOR, AND and OR as controlled operations, where one input is chosen as the control input set and the other bit as the input to be processed depending on the state of the control. Then, all of these gates have one control value that ignores the input (x) and outputs a constant value, while the other control value lets the input pass (maybe complemented): : \begin{align} \operatorname{NAND}(x,0) &= 1 & \operatorname{NAND}(x,1) & = \bar{x} \\ \operatorname{NOR} (x,0) &= \bar{x} & \operatorname{NOR}(x,1) & = 0 \\ \operatorname{AND} (x,0) &= 0 & \operatorname{AND}(x,1) & = {x} \\ \operatorname{OR} (x,0) &= x & \operatorname{OR} (x,1) & = 1 \\ \end{align} Essentially, they can all be used as switches that either set a specific value or let an input value pass.
SR NOR latch s. Red and black mean logical '1' and '0', respectively. The SR NOR latch consists of two parallel NOR gates where the output of each NOR is also fanned out into one input of the other NOR, as shown in the figure. We call these output-to-input connections
feedback inputs, or simply
feedbacks. The remaining inputs we will use as
control inputs as explained above. Notice that at this point, because everything is symmetric, it does not matter to which inputs the outputs are connected. We now break the symmetry by choosing which of the remaining control inputs will be our set and reset and we can call
set NOR the NOR gate with the set control and
reset NOR the NOR with the reset control; in the figures the set NOR is the bottom one and the reset NOR is the top one. The output of the reset NOR will be our stored bit Q, while we will see that the output of the set NOR stores its complement . To derive the behavior of the SR NOR latch, consider S and R as control inputs and remember that, from the equations above, set and reset NOR with control 1 will fix their outputs to 0, while set and reset NOR with control 0 will act as a NOT gate. With this it is now possible to derive the behavior of the SR latch as simple conditions (instead of, for example, assigning values to each line see how they propagate): • While the R and S are both zero, both R NOR and S NOR simply impose the feedback being the complement of the output, this is satisfied as long as the outputs are the complement of each other. Thus the outputs Q and are maintained in a constant state, whether Q=0 or Q=1. • If S=1 while R=0, then the set NOR will fix =0, while the reset NOR will adapt and set Q=1. Once S is set back to zero the values are maintained as explained above. • Similarly, if R=1 while S=0, then the reset NOR fixes Q=0 while the set NOR with adapt =1. Again the state is maintained if R is set back to 0. • If R=S=1, the NORs will fix both outputs to 0, which is not a valid state storing complementary values. :
Note: X means don't care
, that is, either 0 or 1 is a valid value. The R = S = 1 combination is called a
restricted combination or a
forbidden state because, as both NOR gates then output zeros, it breaks the logical equation Q =
not . The combination is also inappropriate in circuits where
both inputs may go low
simultaneously (i.e. a transition from
restricted to
hold). The output could remain in a
metastable state and may eventually lock at either 1 or 0 depending on the propagation time relations between the gates (a
race condition). To overcome the restricted combination, one can add gates to the inputs that would convert (S, R) = (1, 1) to one of the non-restricted combinations. That can be: • Q = 1 (1, 0) – referred to as an
S (dominated)-latch • Q = 0 (0, 1) – referred to as an
R (dominated)-latch This is done in nearly every
programmable logic controller. • Hold state (0, 0) – referred to as an
E-latch Alternatively, the restricted combination can be made to
toggle the output. The result is the
JK latch. The characteristic equation for the SR latch is: : Q_\text{next} = \bar{R}Q + \bar{R}S or Q_\text{next} = \bar{R}(Q + S). where A + B means (A or B), AB means (A and B) Another expression is: : Q_\text{next} = S + \bar{R}Q with SR = 0
NAND latch The circuit shown below is a basic NAND latch. The inputs are also generally designated and for Set and Reset respectively. Because the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit (or active low). The circuit uses the same feedback as SR NOR, just replacing NOR gates with NAND gates, to
remember and retain its logical state even after the controlling input signals have changed. Again, recall that a 1-controlled NAND always outputs 0, while a 0-controlled NAND acts as a NOT gate. When the S and R inputs are both high, feedback maintains the Q outputs to the previous state. When either is zero, they fix their output bits to 0 while to other adapts to the complement. ==0 produces the invalid state.
SR AND-OR latch From a teaching point of view, SR latches drawn as a pair of cross-coupled components (transistors, gates, tubes, etc.) are often hard to understand for beginners. A didactically easier explanation is to draw the latch as a single feedback loop instead of the cross-coupling. The following is an SR latch built with an
AND gate with one
inverted input and an
OR gate. Note that the inverter is not needed for the latch functionality, but rather to make both inputs high-active. : Note that the SR AND-OR latch has the benefit that S = 1, R = 1 is well defined. In above version of the SR AND-OR latch it gives priority to the R signal over the S signal. If priority of S over R is needed, this can be achieved by connecting output Q to the output of the OR gate instead of the output of the AND gate. The SR AND-OR latch is easier to understand, because both gates can be explained in isolation, again with the control view of AND and OR from above. When neither S or R is set, then both the OR gate and the AND gate are in "hold mode", i.e., they let the input through, their output is the input from the feedback loop. When input S = 1, then the OR gate outputs 1, regardless of the other input from the feedback loop ("set mode"). When input R = 1 then the AND gate outputs 0, regardless of the other input from the feedback loop ("reset mode"). And since the AND gate takes the output of the OR gate as input, R has priority over S. Latches drawn as cross-coupled gates may look less intuitive, as the behavior of one gate appears to be intertwined with the other gate. The standard NOR or NAND latches could also be re-drawn with the feedback loop, but in their case the feedback loop does not show the same signal value throughout the whole feedback loop. However, the SR AND-OR latch has the drawback that it would need an extra inverter, if an inverted Q output is needed. Note that the SR AND-OR latch can be transformed into the SR NOR latch using logic transformations: inverting the output of the OR gate and also the 2nd input of the AND gate and connecting the inverted Q output between these two added inverters; with the AND gate with both inputs inverted being equivalent to a NOR gate according to
De Morgan's laws.
JK latch The JK latch is much less frequently used than the JK flip-flop. The JK latch follows the following state table: : Hence, the JK latch is an SR latch that is made to
toggle its output (oscillate between 0 and 1) when passed the input combination of 11. Unlike the SR flip-flop, the 11 input combination for the JK latch is not very useful because there is no clock that directs toggling.
Gated latches and conditional transparency Latches are designed to be
transparent. That is, input signal changes cause immediate changes in output. Additional logic can be added to a transparent latch to make it
non-transparent or
opaque when another input (an
enable input) is not asserted. When several
transparent latches follow each other, if they are all transparent at the same time, signals will propagate through them all. However, following a
transparent-high latch by a
transparent-low latch (or vice-versa) causes the state and output to only change on clock edges, forming what is called a
master–slave flip-flop.
Gated SR latch gates (on left) and
NOR gates (on right) A
gated SR latch can be made by adding a second level of NAND gates to an
inverted SR latch. The extra NAND gates further invert the inputs so a
latch becomes a
gated SR latch (a
SR latch would transform into a
gated latch with inverted enable). Alternatively, a
gated SR latch (with non-inverting enable) can be made by adding a second level of AND gates to a
SR latch. With E high (
enable true), the signals can pass through the input gates to the encapsulated latch; all signal combinations except for (0, 0) =
hold then immediately reproduce on the (Q, ) output, i.e. the latch is
transparent. With E low (
enable false) the latch is
closed (opaque) and remains in the state it was left the last time E was high. A periodic
enable input signal may be called a
write strobe. When the
enable input is a
clock signal, the latch is said to be
level-sensitive (to the level of the clock signal), as opposed to
edge-sensitive like flip-flops below.
Gated D latch This latch exploits the fact that, in the two active input combinations (01 and 10) of a gated SR latch, R is the complement of S. The input NAND stage converts the two D input states (0 and 1) to these two input combinations for the next latch by inverting the data input signal. The low state of the
enable signal produces the inactive
11 combination. Thus a gated D-latch may be considered as a
one-input synchronous SR latch. This configuration prevents application of the restricted input combination. It is also known as
transparent latch,
data latch, or simply
gated latch. It has a
data input and an
enable signal (sometimes named
clock, or
control). The word
transparent comes from the fact that, when the enable input is on, the signal propagates directly through the circuit, from the input D to the output Q. Gated D-latches are also
level-sensitive with respect to the level of the clock or enable signal. Transparent latches are typically used as I/O ports or in asynchronous systems, or in synchronous two-phase systems (
synchronous systems that use a
two-phase clock), where two latches operating on different clock phases prevent data transparency as in a master–slave flip-flop. The truth table below shows that when the
enable/
clock input is 0, the D input has no effect on the output. When E/C is high, the output equals D. File:D-Type Transparent Latch.svg|alt=Schematic diagram|A gated D latch based on an NAND latch File:D-type Transparent Latch (NOR).svg|A gated D latch based on an SR NOR latch File:GatedDLatch-lowres.gif|An animated gated D latch. Black and white mean logical '1' and '0', respectively. File:Multiplexer-based latch using transmission gates.svg|A gated D latch in
pass transistor logic, similar to the ones in the CD4042 or the CD74HC75 integrated circuits
Earle latch The classic gated latch designs have some undesirable characteristics. They require
dual-rail logic or an inverter. The input-to-output propagation may take up to three gate delays. The input-to-output propagation is not constant – some outputs take two gate delays while others take three. Designers looked for alternatives. A successful alternative is the Earle latch. It requires only a single data input, and its output takes a constant two gate delays. In addition, the two gate levels of the Earle latch can, in some cases, be merged with the last two gate levels of the circuits driving the latch because many common computational circuits have an OR layer followed by an AND layer as their last two levels. Merging the latch function can implement the latch with no additional gate delays. The Earle latch is hazard free. If the middle NAND gate is omitted, then one gets the
polarity hold latch, which is commonly used because it demands less logic. However, it is susceptible to
logic hazard. Intentionally skewing the clock signal can avoid the hazard. The D flip-flop can be viewed as a memory cell, a
zero-order hold, or a
delay line. Truth table: : (
X denotes a ''
don't care'' condition, meaning the signal is irrelevant) Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D and clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops. Setting S = R = 0 makes the flip-flop behave as described above. Here is the truth table for the other possible S and R configurations: : These flip-flops are very useful, as they form the basis for
shift registers, which are an essential part of many electronic devices. The advantage of the D flip-flop over the D-type
transparent latch is that the signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock event. An exception is that some flip-flops have a
reset signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the clock. The above circuit shifts the contents of the register to the right, one bit position on each active transition of the clock. The input X is shifted into the leftmost bit position.
Classical positive-edge-triggered D flip-flop This circuit consists of two stages implemented by
NAND latches. The input stage (the two latches on the left) processes the clock and data signals to ensure correct input signals for the output stage (the single latch on the right). If the clock is low, both the output signals of the input stage are high regardless of the data input; the output latch is unaffected and it stores the previous state. When the clock signal changes from low to high, only one of the output voltages (depending on the data signal) goes low and sets/resets the output latch: if D = 0, the lower output becomes low; if D = 1, the upper output becomes low. As long as the clock signal stays high, these input-stage outputs keep their states regardless of the data input and force the output latch to stay in the corresponding state, as the input logical zero (of the output stage) remains active while the clock is high. Any change of the data input while the clock is high will not change the states of the two input-stage latches. Hence the role of the output latch is to store the data only while the clock is low. The circuit is closely related to the
gated D latch as both the circuits convert the two D input states (0 and 1) to two input combinations (01 and 10) for the output latch by inverting the data input signal (both the circuits split the single D signal in two complementary and signals). The difference is that NAND logical gates are used in the gated D latch, while NAND latches are used in the positive-edge-triggered D flip-flop. The role of these latches is to
lock the active output producing low voltage (a logical zero); thus the positive-edge-triggered D flip-flop can also be thought of as a gated D latch with latched input gates.
Master–slave edge-triggered D flip-flop A master–slave D flip-flop is created by connecting two
gated D latches in series, and inverting the
enable input to one of them. It is called master–slave because the master latch controls the slave latch's output value Q and forces the slave latch to hold its value whenever the slave latch is enabled, as the slave latch always copies its new value from the master latch and changes its value only in response to a change in the value of the master latch and clock signal. For a positive-edge triggered master–slave D flip-flop, when the clock signal is low (logical 0) the
enable seen by the first or
master D latch (the inverted clock signal) is high (logical 1). This allows the
master latch to store the input value when the clock signal transitions from low to high. As the clock signal goes high (0 to 1) the inverted
enable of the first latch goes low (1 to 0) and the value seen at the input to the master latch is
locked. Nearly simultaneously, the twice inverted
enable of the second or
slave D latch transitions from low to high (0 to 1) with the clock signal. This allows the signal captured at the rising edge of the clock by the now
locked master latch to pass through the
slave latch. When the clock signal returns to low (1 to 0), the output of the
slave latch is
locked, and the value seen at the last rising edge of the clock is held while the
master latch begins to accept new values in preparation for the next rising clock edge. Removing the leftmost inverter in the circuit creates a D-type flip-flop that strobes on the
falling edge of a clock signal. This has a truth table like this: :
Dual-edge-triggered D flip-flop Flip-Flops that read in a new value on the rising and the falling edge of the clock are called dual-edge-triggered flip-flops. Such a flip-flop may be built using two single-edge-triggered D-type flip-flops and a multiplexer, or by using two single-edge triggered D-type flip-flops and three XOR gates.
Edge-triggered dynamic D storage element An efficient functional alternative to a D flip-flop can be made with dynamic circuits (where information is stored in a capacitance) as long as it is clocked often enough; while not a true flip-flop, it is still called a flip-flop for its functional role. While the master–slave D element is triggered on the edge of a clock, its components are each triggered by clock levels. The
edge-triggered D flip-flop, as it is called even though it is not a true flip-flop, does not have the master–slave properties. Edge-triggered D flip-flops are often implemented in integrated high-speed operations using
dynamic logic. This means that the digital output is stored on parasitic device capacitance while the device is not transitioning. This design facilitates resetting by simply discharging one or more internal nodes. A common dynamic flip-flop variety is the true single-phase clock (TSPC) type which performs the flip-flop operation with little power and at high speeds. However, dynamic flip-flops will typically not work at static or low clock speeds: given enough time, leakage paths may discharge the
parasitic capacitance enough to cause the flip-flop to enter invalid states.
T flip-flop If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristic
equation: : Q_\text{next} = T \oplus Q = T\overline{Q} + \overline{T}Q (expanding the
XOR operator) and can be described in a
truth table: : When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has application in various types of digital
counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T) or a D flip-flop (T input XOR Qprevious drives the D input).
JK flip-flop The JK flip-flop augments the behavior of the SR flip-flop (J: Set, K: Reset) by interpreting the J = K = 1 condition as a
flip or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 maintains the current state. To synthesize a D flip-flop, simply set K equal to the complement of J (input J will act as input D). Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop. The characteristic equation of the JK flip-flop is: : Q_\text{next} = J\overline Q + \overline KQ and the corresponding truth table is: : ==Timing considerations==