The floorplanning design stage consists of various steps with the aim of finding floorplans that allow a
timing-clean routing and spread power consumption over the whole chip. •
Chip Area Estimation: The dimensions and aspect ratio of the chip area are determined. The estimation considers the space required to place macros, standard cells and I/O ports while also leaving enough space for routing resources to enable a successful
place and route design flow. Usually a core utilization U = \frac{A_ + A_}{A_} of 60%-70% is targeted. •
I/O Pad Positioning: Input/Output Pads usually need to be positioned along the periphery of the chip. Near the I/O Pads space for
line drivers needs to be reserved to minimize delay and signal degradation. •
Macro Placement: During macro placement large functional blocks with a fixed size and fixed pins such as
memory arrays,
clock generators or custom components need to be placed within the floorplan's outline. Effective macro placement minimizes the length of timing critical paths, avoids routing congestion and ensures thermal balance. although they might be of multi-row height. The height of the standard cell rows determines the available routing resources per row while also influencing the power. •
Power / Ground Structures: Obtaining a power/
ground network is not always included in the floorplanning stage. There are however approaches to cosynthesize floorplans and
P/G networks based on the idea that if macros and I/O pads are fixed, a power grid analysis is possible. ==Mathematical models==