The 2005 presented FR1000 uses a core with 8-way 256-bit
VLIW (
MIMD) filling its
superpipeline as well as a 4-unit
superscalar architecture (
integer (ALU)-,
floating-point- and two media-processor-units), further increasing its
peak performance of each core to up to 28
instructions per clock cycle. Like other VLIW-architectures 1 way is needed to load the next 256-bit instruction: 7-ways usable. Due to the used 4-way
single instruction, multiple data (SIMD)
vector processor-core, it counts to up to 112
data-operations per cycle and core. The included 4-way vector processor units are a
32-bit integer arithmetic logic unit and
floating point unit as well as a
16-bit media-processor, which can process up to twice the operations in parallel. The included integer- and floating-point unit enables the FR-V to execute complex tasks fully independent without need for help from a
control unit; for example the
Nikon Expeed needs only a slowly clocked, quite simple
Fujitsu FR controller as the main control unit for all included FR-V,
DSP and
GPU processors and
data communication and other modules. Some processors have integrated
memory management unit (MMU), allowing to run
virtual multitasking operating systems (also
real-time operating systems) with hardware
memory protection. ==Applications==