For the
CMOS process, FEOL contains all fabrication steps needed to form isolated CMOS elements: • Selecting the type of
wafer to be used;
Chemical-mechanical planarization (CMP) and cleaning of the wafer. •
Shallow trench isolation (STI) (or
LOCOS in early processes with
feature size > 0.25 μm); • Well formation; •
Gate module formation; •
Source and drain module formation. Finally, the surface is treated to prepare the contacts for the subsequent metallization. This concludes the FEOL process, that is, all devices have been built. Following these steps, the devices must be connected electrically as per the nets to build the electrical circuit. This is done in the
back end of line (BEOL). BEOL is thus the second portion of IC fabrication where the individual devices are connected. ==See also==