Avionics Full-Duplex Switched Ethernet

Many commercial aircraft use the ARINC 429 standard developed in 1977 for safety-critical applications. ARINC 429 utilizes a unidirectional bus with a single transmitter and up to twenty receivers. A data word consists of 32 bits communicated over a twisted pair cable using the bipolar return-to-zero modulation. There are two speeds of transmission: high speed operates at 100 kbit/s and low speed operates at 12.5 kbit/s. ARINC 429 operates in such a way that its single transmitter communicates in a point-to-point connection, thus requiring a significant amount of wiring which amounts to added weight. Another standard, ARINC 629, introduced by Boeing for the 777 provided increased data speeds of up to 2 Mbit/s and allowing a maximum of 120 data terminals. This ADN operates without the use of a bus controller thereby increasing the reliability of the network architecture. The drawback is that it requires custom hardware which can add significant cost to the aircraft. Because of this, other manufacturers did not openly accept the ARINC 629 standard. AFDX was designed as the next-generation aircraft data network. Basing on standards from the IEEE 802.3 committee (commonly known as Ethernet) allows commercial off-the-shelf hardware to reduce costs and development time. AFDX is one implementation of deterministic Ethernet defined by ARINC Specification 664 Part 7. AFDX was developed by Airbus Industries for the A380, Multiple switches can be bridged together in a cascaded star topology. This type of network can significantly reduce wire runs, thus the weight of the aircraft. In addition, AFDX can provide quality of service and dual link redundancy. Building on the experience from the A380, the Airbus A350 also uses an AFDX network, with avionics and systems supplied by Rockwell Collins. and Vector Informatik GmbH. ==Overview==

AFDX adopted concepts such as the token bucket from the telecom standards, Asynchronous Transfer Mode (ATM), to fix the shortcomings of IEEE 802.3 Ethernet. By adding key elements from ATM to those already found in Ethernet, and constraining the specification of various options, a highly reliable full-duplex deterministic network is created providing guaranteed bandwidth and quality of service (QoS). Through the use of full-duplex Ethernet, the possibility of transmission collisions is eliminated. The network is designed in such a way that all critical traffic is prioritized using QoS policies so delivery, latency, and jitter are all guaranteed to be within set parameters. A highly intelligent switch, common to the AFDX network, is able to buffer transmission and reception packets. Through the use of twisted pair or fiber optic cables, full-duplex Ethernet uses two separate pairs or strands for transmitting and receiving the data. AFDX extends standard Ethernet to provide high data integrity and deterministic timing. Further a redundant pair of networks is used to improve the system integrity (although a virtual link may be configured to use one or the other network only). It specifies interoperable functional elements at the following OSI reference model layers: • Data link (MAC and virtual link addressing concept); • Network (IP and ICMP); • Transport (UDP and optionally TCP) • Application (network) (sampling, queuing, SAP, TFTP and SNMP). The main elements of an AFDX network are: • AFDX end systems • AFDX switches • AFDX links ==Virtual links==

The central feature of an AFDX network are its virtual links (VL). In one abstraction, it is possible to visualise the VLs as an ARINC 429 style network each with one source and one or more destinations. Virtual links are unidirectional logic paths from the source end-system to all of the destination end-systems. Unlike that of a traditional Ethernet switch which switches frames based on the Ethernet destination or MAC address, AFDX routes packets using a virtual link ID, which is carried in the same position in an AFDX frame as the MAC destination address in an Ethernet frame. However, in the case of AFDX, this virtual link ID identifies the data carried rather than the physical destination. The virtual link ID is a 16-bit unsigned integer value that follows a constant 32-bit field. The switches are designed to route an incoming frame from one, and only one, end system to a predetermined set of end systems. There can be one or more receiving end systems connected within each virtual link. Each virtual link is allocated dedicated bandwidth [sum of all VL bandwidth allocation gap (BAG) rates x MTU] with the total amount of bandwidth defined by the system integrator. However, total bandwidth cannot exceed the maximum available bandwidth on the network. Bi-directional communications must therefore require the specification of a complementary VL. Each VL is frozen in specification to ensure that the network has a designed maximum traffic, hence determinism. Also the switch, having a VL configuration table loaded, can reject any erroneous data transmission that may otherwise swamp other branches of the network. Additionally, there can be sub-virtual links (sub-VLs) that are designed to carry less critical data. Sub-virtual links are assigned to a particular virtual link. Data are read in a round-robin sequence among the virtual links with data to transmit. Also sub-virtual links do not provide guaranteed bandwidth or latency due to the buffering, but AFDX specifies that latency is measured from the traffic regulator function anyway. ==BAG rate==

BAG stands for bandwidth allocation gap, this is one of the main features of the AFDX protocol. This is the maximum rate data can be sent, and it is guaranteed to be sent at that interval. When setting the BAG rate for each VL, care must be taken so there will be enough bandwidth for other VL's and the total speed cannot exceed 100 Mbit/s. ==Switching of virtual links==

Each switch has filtering, policing, and forwarding functions that should be able to process at least 4096 VLs. Therefore, in a network with multiple switches (cascaded star topology), the total number of virtual links is nearly limitless. There is no specified limit to the number of virtual links that can be handled by each end system, although this will be determined by the BAG rates and maximum frame size specified for each VL versus the Ethernet data rate. However, the number of sub-VLs that may be created in a single virtual link is limited to four. The switch must also be non-blocking at the data rates that are specified by the system integrator, and in practice this may mean that the switch shall have a switching capacity that is the sum of all of its physical ports. Since AFDX utilizes the Ethernet protocol at the MAC layer, it is possible to use high performance COTS switches with Layer 2 routing as AFDX switches for testing purposes as a cost-cutting measure. However, some features of a real AFDX switch may be missing, such as traffic policing and redundancy functions. ==Usage==

The AFDX bus is used in Airbus A380, Boeing 787, Airbus A400M, Airbus A350, Sukhoi Superjet 100, ATR 42, ATR 72 (-600), AgustaWestland AW101, AgustaWestland AW189, AgustaWestland AW169, Irkut MC-21, Bombardier Global Express, Airbus A220, Learjet 85, Comac ARJ21, Comac C919 and AgustaWestland AW149. ==References==