GE 645

The basic system configuration consisted of a combination of 4 basic modules these were: • Processor • System Controller • Generalized I/O Controller (GIOC) • Extended Memory Unit (EMU) The System Controller Modules (SCM) effectively acted as the heart of the system. These were passive devices which was connected to each active device (Processor, GIOC, EMU) and provided the following: • Core Memory - 1 microsecond memory in size capacities of 32K, 64K or 128K of 36-bit words. • Centralized point for forwarding control signals from one active module to another • System Clock and the ability to issue interrupts to the processors. Compared to the rest of the 600 series the 645 did not use the standard IOC's (input/output controllers) for I/O. Nor did it use the DATANET-30 front end processor for communications. Instead both sets of functionality was combined into one unit called a GIOC (Generalized I/O Controller) which provided dedicated channels for both Peripheral (Disc/Tape) and Terminal I/O. The GIOC acted as an Active Device and was directly connected to memory via dedicated links to each System Controller that was present in a specific configuration. The Extended Memory Unit, though termed a drum, was in reality a large fixed-head hard disk with one head per track, this was a OEM product from Librascope. The EMU consisted of 4,096 tracks providing 4MW (megawords) of storage (equivalent to 16MB). Each track had a dedicated read/write head, these were organised into groups of 16 "track sets" which are used to read/write a sector. A sector is the default unit of data allocation in the EMU and is made up of 80 words, of which 64 words are data and the remaining 16 were used as a guard band. The average transfer rate between the EMU and memory was 470,000 words per second, all transfers were 72-bits (two words) wide, with it taking 6.7μs to transfer 4 words. The unit had a rotational speed of 1,725 rpm, which ensured an average latency of 17.4 milliseconds. ==Architecture==

Processor Modes The GE-645 has two modes of Instruction Execution (Master and Slave) inherited from the GE-635, however it also adds another dimension by having two modes of memory addressing (Absolute and Appending). When the process is executing in Absolute Mode addressing is limited to 218 words of memory and any instructions are executed in Master mode. In comparison Append Mode calculates the address using "Appending Words" with an address space of 224 words and with instruction execution occurring in either Master or Slave modes. • Registers point to most recently used segment (Segment Descriptor Word) or most recently used Page (Page Table) • Performs the function of what would now be classed as a TLB. • Control Unit: • Performs all control functions • Performs Address modification • Controls the processor mode (master, slave, absolute) • Interrupt recognition/handling • Opcode decoding • Operations Unit: • Performs fractional and integer divisions and multiplications. • Performs automatic alignment of floating-point numbers for addition and subtraction. • Performs inverted divisions on floating-point numbers. • Performs automatic normalization of floating-point resultants. • Performs shifts. • Performs indicator register loading and storing. • Performs timer register loading and decrementing. One of the key differences from the GE 635 was the addition of "appending unit" (APU) which was used to implement a hybrid "Paged Segmentation" model of virtual memory. The APU was also used to implement a single-level store which is one of the fundamental abstraction that Multics is built around. The instruction format was also extended with the previously unused bit 29 controlling whether the operand address of an instruction used an 18-bit format (bit 29 = 0) or one that was made up of a 3-bit Base Register address with a 15-bit offset (bit 29 = 1). The instruction format with bit 29 set to 1 is: 1 1 2 2 2 2 3 3 0 2 3 7 8 6 7 8 9 0 5 +---+---------------+---------+-+-+-+------+ |BR | Y | OP |0|I|1| Tag | +---+---------------+---------+-+-+-+------+ • B is the base register field • Y is the address field (15 bits), addressing 32KW • OP is the opcode (9 bits), the additional bit 27 is the opcode extension bit. • I is the interrupt inhibit bit. • Tag indicates the type of address modification to be performed; some additional tags are supported by the GE 645. these could operate in either "paired" or "unpaired" modes. The later Honeywell 6180 changed these to 8 pointer registers. Each abr was 24-bits wide consisting of 18 bits for an address and 6 bits for control functions. One bit of the control functions field indicates where an abr is "internal" or "external". If an abr is internal, another 3-bit subfield of the control functions field specifies another abr with which this abr is paired; that other abr is external, with the external abr containing a segment number in the address field and the internal abr containing an offset within the segment specified by the external abr. the standard Multics practice was to label these registers as follows: • ap for abr 0 • ab for abr 1 • bp for abr 2 • bb for abr 3 • lp for abr 4 • lb for abr 5 • sp for abr 6 • sb for abr 7 The naming scheme is based around the following: • a for argument-list pointer • b for general base • l for linkage-segment pointer • s for stack-segment pointer The 8 pointer registers in the Honeywell 6180 and its successors served the same purpose as the 4 paired base registers in the GE-645, referring to an offset within a segment. ==History==

CTSS had originated in the MIT Computation Center using a IBM 709 and was first demonstrated in November 1961, it was subsequently upgraded to a 7090 in 1962, and finally to a 7094 in 1963. This required modification to these standard systems via the addition of a number of RPQ's which among others added two banks of memory and bank-switching between user and supervisor mode, i.e. programs running in the A-core memory bank had access to instructions that programs running in the B-core bank did not. Project MAC formally began with signing of contract with ARPA on the 1st of July 1963. By October 1963 they had received a dedicated 7094 to run CTSS under, this was termed the "Red Machine" due to it having red side panels. It was made clear that Project MAC was looking for a development partner given the considerable hardware modifications that would be required to meet their requirements, which were specified as: • User Programs having read/write protection. • That privileged instructions would not be accessible to end user programs • At least the ability to address 256KW of memory directly. • Native multiprocessing capability with all processors been of equivalent functional level • Effective support for telecommunications which could handle both conventional telephone lines as well as high speed data links that could run graphic display terminals such as the MIT-developed Kludge graphical terminal. • Mass storage units, including a fast drum that could be used as a paging device. • Hardware support for both segmentation and paging with support for a content addressable memory (CAM) so as to reduce virtual memory overhead. They proceeded to visit among others Burroughs, CDC, DEC, General Electric, IBM and Sperry Univac. Of these GE and IBM showed the strongest interest. so that development and checkout of Multics could occur in parallel. This process involved creating a tape on the CTSS system which would be inputted to GECOS on the 635 system in MIT so that it would run under the 6.36 simulator; the resulting output would be carried back via tape to CTSS for debugging/analysis. This simulated environment was replaced by the first 645 hardware in 1967. The GECOS operating system was fully replaced by Multics in 1969 with the Multics supervisor separated by protection rings with "gates" allowing access from user mode. A later generation in the form of the 645F (F for follow-on) wasn't completed by the time the division was sold to Honeywell, and became known as the Honeywell 6180. The original access control mechanism of the GE/Honeywell 645 were found inadequate for high speed trapping of access instructions and the re-implementation in the 6180 solved those problems. The bulk of these computers running time-sharing on Multics were installed at the NSA and similar governmental sites. Their usage was limited by the extreme security measures and had limited impact on subsequent systems, other than the protection ring. The hardware protection introduced on this computer and modified on the 6180 was later implemented in the Intel 286 computer processor as a four-layer protection ring, but four rings was found to be too cumbersome to program and too slow to operate. Protection ring architecture is now used only to protect kernel mode from user mode code just as it was in the original use of the 645. ==See also==