The consortium was publicly announced on October 11, 2016. Members include server vendors
Cisco Systems,
Cray,
Dell Technologies,
Hewlett Packard Enterprise,
Huawei,
IBM, and
Lenovo. CPU vendor members include
Advanced Micro Devices,
ARM Holdings,
Broadcom Limited, IBM, and
Marvell. Memory and storage vendor members include
Micron Technology,
Samsung,
Seagate Technology,
SK Hynix, and
Western Digital. Other members include
IDT Corporation, IntelliProp,
Mellanox Technologies,
Microsemi,
Red Hat, and
Xilinx. Analysts noted the absence of
Intel, which announced an inter-connect technology of its own called
Omni-Path a year before, and
Nvidia, with its own
NVLink technology.
SNIA, and
DMTF. The effort followed years of delays with product availability for version 4.0 of
PCI Express. At about the same time, yet another consortium formed to work on an open specification for the
Coherent Accelerator Processor Interface (CAPI). The first version of the GenZ Core specifications was published in 2018; it defined a physical link with both
PCI Express and
50 Gigabit Ethernet physical layer (PHY) standards. The Gen-Z protocol allows for asymmetric links with more bandwidth in one direction, and supports connection topologies like point to point links, daisy-chaining, and switched fabrics. The basic operations consist of simple loads and stores with the addition of modular extensions. ==Collaboration with CXL==