System architecture was documented in the
305 RAMAC Manual of Operation. The 305 was a character-oriented
variable "word" length decimal (
BCD) computer with a
drum memory rotating at 6000
RPM that held 3200
alphanumeric characters. A
core memory buffer of 100 characters was used for temporary storage during data transfers. Each character was six bits plus one
odd parity bit ("R") composed of two zone bits ("X" and "O") and remaining four binary bits for the value of the digit in the following format: X O 8 4 2 1 R
Instructions could only be stored on 20 tracks of the drum memory and were fixed length (10 characters), in the following format: :T1 A1 B1 T2 A2 B2 M N P Q
Fixed-point data "words" could be any size from one decimal digit up to 100 decimal digits, with the X bit of the least significant digit storing the sign (
signed magnitude). Data records could be any size from one character up to 100 characters.
Drum memory The drum memory was organized into 32 tracks of 100 characters each. The color code of this table is: • Yellow – Storage • Blue – Arithmetic • Green – Input/output • Red – Special function L and M select the same track, containing ten 10-character "
Accumulators". As a destination
L specifies addition,
M specifies subtraction. (Numbers in these accumulators were stored in
ten's complement form, with the X bit of the most significant digit storing the sign. The sign of each accumulator was also held in a
relay. However the 305 automatically converted between its standard signed magnitude format and this format without the need for special programming.) J,
R, and - do not select tracks on the drum, they specify other sources and destinations.
Jumps The 305's instruction set does not include any jumps, instead these are programmed on the control panel: • Unconditional jump – the program exit code (P field) specifies a
Program exit hub on the control panel, which has a wire plugged into it and, via distributors, to
Program entry hubs specifying the first, second and third address digit of the instruction to jump to. • Conditional jump – the program exit code (P field) specifies a
Program exit hub on the control panel, which has a wire plugged into it and the appropriate
Condition selector common hub to be tested, the corresponding two
Condition selector output hubs have wires plugged into them and the
Program entry hubs specifying the instructions to jump to or the
Program advance hub to continue in sequence. Complicated conditions involving many
Condition selectors could be wired to execute in a single instruction (e.g., Testing the sign and zero states of multiple accumulators), with one of several
Program entry hubs activated. • Multi-way jump – the destination track (T2 field) is set to - and the appropriate
Character selector hubs on the control panel have wires plugged into them and the
Program entry hubs specifying the instructions to jump to or the
Program advance hub to continue in sequence.
Timing All timing signals for the 305 were derived from a factory recorded
clock track on the drum. The clock track contained 816 pulses 12 μs apart with a 208 μs gap for sync. Reading or writing a character took 96 μs. The 305's typical instruction took three revolutions of the drum (30 ms): one (
I phase) to fetch the instruction, one (
R phase) to read the source operand and copy it to the core buffer, and one (
W phase) to write the destination operand from the core buffer. If the P field (Program exit code) was not blank, then two (
D phase and
P phase) additional revolutions of the drum (20 ms) were added to the execution time to allow relays to be picked. The
Improved Processing Speed option could be installed that allowed the three instruction phases (
IRW) to immediately follow each other instead of waiting for the next revolution to start; with this option and well optimized code and operand placement a typical instruction could execute in as little as one revolution of the drum (10 ms). Certain instructions though took far longer than the typical 30 ms to 50 ms. For example, multiply took six to nineteen revolutions of the drum (60 ms to 190 ms) and divide (an option) took ten to thirty-seven revolutions of the drum (100 ms to 370 ms). Input/Output instructions could interlock the processor for as many revolutions of the drum as needed by the hardware. ==Hardware implementation==