The POWER6 is a
dual-core processor. Each core is capable of two-way
simultaneous multithreading (SMT). The POWER6 has approximately 790 million transistors and is 341 mm2 large fabricated on a
65 nm process. A notable difference from
POWER5 is that the POWER6 executes instructions in-order instead of
out-of-order. This change often requires software to be recompiled for optimal performance, but the POWER6 still achieves significant performance improvements over the POWER5+ even with unmodified software, according to the lead engineer on the POWER6 project. Each core has a 64 KB, four-way set-associative instruction cache and a 64 KB data cache of an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle. Each core has semi-private 4
MiB unified
L2 cache, where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB
L3 cache which is off die, using an 80 GB/s bus. POWER6 can connect to up to 31 other processors using two inter node links (50 GB/s), and supports up to 10 logical partitions per core (up to a limit of 254 per system). There is an interface to a service processor that monitors and adjusts performance and power according to set parameters. IBM also makes use of a 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 μm wide and 1.2 μm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.
POWER6+ The slightly enhanced
POWER6+ was introduced in April 2009, but had been shipping in
Power 560 and 570 systems since October 2008. It added more memory keys for secure
memory partition, a feature taken from IBM's
mainframe processors. == Products ==