IBM ROMP

The ROMP is a reduced instruction set computer (RISC) microprocessor designed by IBM in the late 1970s. It is also known as the Research OPD Miniprocessor and 032. The ROMP was originally developed for office equipment and small computers, intended as a follow-on to the mid-1970s IBM OPD Mini Processor microprocessor, which was used in the IBM Office System/6 word-processing system. The first examples became available in 1981, and it was first used commercially in the IBM RT PC announced in January 1986. For a time, the RT PC was planned to be a personal computer, with ROMP replacing the Intel 8088 found in the IBM Personal Computer. However, the RT PC was later repositioned as an engineering and scientific workstation computer. A later CMOS version of the ROMP was first used in the coprocessor board for the IBM 6152 Academic System introduced in 1988, and it later appeared in some models of the RT PC.

History

The architectural work on the ROMP began in late spring of 1977, as a spin-off of IBM Research's 801 RISC processor (hence the "Research" in the acronym). Most of the architectural changes were for cost reduction, such as adding 16-bit instructions for byte-efficiency. The original ROMP had a 24-bit architecture, but the instruction set was changed to 32 bits a few years into the development. The first chips were ready in early 1981, making ROMP the first industrial RISC. The processor was revealed at the International Solid-State Circuits Conference in 1984 ==Architecture==

Architecture

The ROMP's architecture was based on the original version of the IBM Research 801 minicomputer. The main differences were a larger word size (32 bits instead of 24), and the inclusion of virtual memory. The architecture supported 8-, 16-, and 32-bit integers, 32-bit addressing, and a 40-bit virtual address space. It had an instruction pointer register and sixteen 32-bit general-purpose registers. The microprocessor was controlled by 118 simple 16- and 32-bit instructions. The ROMP's virtual memory has a segmented 40-bit (1TB) address space consisting of 4,096 256MB segments. The 40-bit virtual address is formed in the MMU by concatenating a 12-bit segment identifier with 28 low-order bits from a 32-bit ROMP-computed virtual address. The segment identifier is obtained from a set of 16 segment identifiers stored in the MMU, addressed by the four high-order bits of the 32-bit ROMP-computed virtual address. ==Implementation==

Implementation

The ROMP is a scalar processor with a three-stage pipeline. The ROMP had an IBM-developed companion integrated circuit which was code-named Rosetta during development. Rosetta was a memory management unit (MMU), and it provided the ROMP with address translation facilities, a translation lookaside buffer, and a store buffer. The ROMP consists of 45,000 transistors and is 7.65×7.65mm large (58.52mm2), while Rosetta consists of 61,500 transistors and is 9.02×9.02mm large (81.36mm2). Both are packaged in 135-pin ceramic pin grid arrays. A CMOS version of the ROMP and Rosetta (called ROMP-C and Rosetta-C) was later developed. ==References==

Source: Wikipedia ↗

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