IBM System/4 Pi

In 1967, the System/4 Pi family consisted of these basic models: • Model TC (Tactical Computer) - A briefcase-size computer for applications such as missile guidance, helicopters, satellites and submarines. • Model CP (Customized Processor/Cost Performance) - An intermediate-range processor for applications such as aircraft navigation, weapons delivery, radar correlation and mobile battlefield systems. • Model CP-2 (Cost Performance - Model 2) • Model EP (Extended Performance) - A large-scale data processor for applications requiring real-time processing of large volumes of data, such as crewed spacecraft, airborne warning and control systems and command and control systems. Model EP used an instruction subset of IBM System/360 (Model 44) - user programs could be checked on System/360 The Skylab space station employed the model TC-1, which had a 16-bit word length and 16,384 words of memory with a custom input/output assembly. Skylab had two, redundant, TC-1 computers: a prime (energized) and a backup (non energized.) There would be an automatic switchover (taking on the order of one second) to the backup in the event of a critical failure of the prime. A total of twelve were delivered to NASA by 1972. Two were flown on Skylab in 1973-1974; the others were used for testing and mission simulators. The software management effort was led by Harlan Mills and Fred Brooks. The Skylab flight software development process incorporated many lessons learned during the IBM System/360 Operating System project, as described in Brooks' 1975 book The Mythical Man-Month. ==Advanced Processor==

The AP-101, being the top-of-the-line of the System/4 Pi range, shares its general architecture with the System/360 mainframes. There were a number of variants of the AP101. The Offensive Avionics System, a retrofit update of the B-52, contains two AP-101C computers. The AP-101C prototypes were delivered in 1978. The Space Shuttle used two variants of the AP-101: the earlier AP-101B and the upgraded AP-101S. The AP-101B was used for a series of Approach and Landing Tests in 1977. The first ascent to orbit was in 1981. The AP-101S first launched in 1991. Each AP-101 on the Shuttle was coupled with an input-output processor (IOP), consisting of one Master Sequence Controller (MSC) and 24 Bus Control Elements (BCEs). The MSC and BCEs executed programs from the same memory system as the main CPU, offloading control of the Shuttle's serial data bus system from the CPU. The AP-101B originally used in the Space Shuttle had magnetic-core memory. The upgrade to the AP-101S in the early 1990s replaced the core with semiconductor memory and reduced the size from two to one chassis. The AP-102 variant design began in 1984. It is a MIL-STD-1750A standard instruction set architecture. It was first used in the F-117A Nighthawk. It was upgraded to the AP-102A in the early 1990s. ==References==