The chip contains 8 processor cores with a deep
superscalar out-of-order pipeline, running with more than 5 GHz clock frequency which is optimized for the demands of heterogenous enterprise-class workloads (e.g: finance, security sensitive applications, applications requiring extreme reliability). The cache and chip-interconnection infrastructure provides 32 MB cache per core and can scale to 32 Telum chips. Unlike other processors, the IBM Telum does not thermal throttle by reducing clock speed; instead it inserts sleep state instructions. The Neural Network Processing Assists (NNPA) instruction performs a variety of tensor instructions useful for neural networks. Telum II adds new functions to NNPA. ==See also==