List of Intel Itanium processors

Merced (180 nm) Steppings: C0, C1 and C2. CPUID: 0007000604h (stepping C0), 0007000704h (stepping C1) or 0007000804h (stepping C2). Transistor count: 25.4 million for CPU, 295 million for the external L3 cache. The FSB data bus is 64 bits wide, not 128 like in Itanium 2. ==Itanium 2 (2002-2007)==

Itanium 2 uses socket PAC611 with a 128 bit wide FSB. The 90 nm CPUs (9000 and 9100 series) bring dual-core chips and an updated microarchitecture adding multithreading and splitting the L2 cache into a 256 KB data cache and 1 MB instruction cache per core (the pre-9000 series L2 cache being a 256 KB common cache). All Itaniums except some 130 nm models are capable of >2-socket SMP. McKinley (180 nm) Stepping: B3. Die size: 421 mm2. Transistor count: 221 million. CPUID: 001F000704h Madison (130 nm) Stepping: B1. Die size: 374 mm2. Transistor count: 410 million. CPUID: 001F010504h. The Madison 9M table contains the 4MB and 6MB successors of the first Madisons. Deerfield The same chip as Madison, but at a lower voltage. Madison 9M (130 nm) Steppings: A1 and A2. Die size: 432 mm2. Transistor count: 592 million. CPUID: 001F020104h (stepping A1) or 001F020204h (stepping A2). 9M is the chip of all the third generation Itanium 2s, irrespective of the amount of enabled cache. Fanwood The same chip as Madison 9M, but restricted to 2-socket and uniprocessor systems. HP mx2 MCM (130 nm) This multi-chip module codenamed Hondo is not an Intel product, but a separate project of Hewlett-Packard to pack two CPUs onto one PAC611 socket. The S-Spec SL75Z was assigned to the chips that Intel sent to HP for use in mx2. Montecito (90 nm) Steppings: C1 and C2. Die size: 596 mm2. Transistor count: 1720 million. CPUID: 0020000504h (stepping C1) or 0020000704h (stepping C2). All processors can support the legacy 400 MT/s FSB. From Montecito onwards all Itaniums are MP-capable. Montvale (90 nm) The chip is similar to Montecito, but the stepping is A1 and the CPUID is 0020010104h. The models with 533 MT/s FSB also support 400 MT/s FSB operation. The processors with the Core level Lock-Step error correction feature were released only in 2008. Even though Intel does not use the "Itanium 2" branding for the 9100-series, it's still grouped with Itanium 2 processors because it uses the same platform and is a minor update on the 9000-series. ==Itanium (2007–2019)==

These later generations of Itanium use socket LGA 1248, the QuickPath Interconnect and Scalable Memory Interconnect having replaced the Front-Side Bus used by Itanium 2. Tukwila (65 nm) Stepping: E0. Die size: 699 mm2. Transistor count: 2046 million. CPUID: 0020020404.All models support: XD bit (an NX bit implementation), Hyper-threading, Turbo Boost, VT-i2 (Itanium Virtualization technology), Intel VT-d, RAS with Advanced Machine Check Architecture, Cache Safe technology, Enhanced Demand Based Switching, ECC, two memory controllers each with two SMI links to memory buffers for DDR3, for a combined memory bandwidth of 34 GB/s and capacity of 256 GB. The QPI bandwidth is 96 GB/s for cache coherency and 24 GB/s for I/O. • • Poulson (32 nm) Stepping: D0. Die size: 544 mm2. Transistor count: 3.1 billion. CPUID: 0021000404.All models support: Itanium New Instructions, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, VT-i3 (Itanium Virtualization technology), Hyper-threading (with Dual-Domain Multithreading), Turbo Boost, Enhanced Intel SpeedStep Technology (EIST), Cache-Safe technology, RAS with Advanced Machine Check Architecture, Instruction Replay technology, ECC, two memory controllers each with two SMI links to memory buffers for DDR3, for a combined memory bandwidth of 45 GB/s and capacity of 512 GB. The QPI bandwidth is 128 GB/s for cache coherency and 32 GB/s for I/O. Kittson (32 nm) The 9700 series, despite nominally having a different stepping (E0 with CPUID 0021000504), is functionally identical with the 9500 series, even having exactly the same bugs, the only difference being the 133 MHz higher frequency of 9760 and 9750 over 9560 and 9550 respectively. Intel had committed to at least one more generation after Poulson, first mentioning Kittson on 14 June 2007. Kittson was supposed to be on a 22 nm process and use the same LGA2011 socket and platform as Xeons. On 31 January 2013 Intel issued an update to their plans for Kittson: it would have the same LGA1248 socket and 32 nm process as Poulson, effectively halting any further development of Itanium processors. ==See also==