Quick Sync was first unveiled at Intel Developer Forum 2010 (September 13) but, according to ''Tom's Hardware'', Quick Sync had been conceptualized five years before that. ; Version 2 (
Ivy Bridge,
Bay Trail) : The
Ivy Bridge microarchitecture included a "next-generation" implementation of Quick Sync. ; Version 3 (
Haswell) : The
Haswell microarchitecture implementation adds
H.262/MPEG-2 Part 2 encoding acceleration., although as of 2023 Intel had explicitly abandoned both this driver and pre-Kaby Lake accelerated VP8 encoding. Starting from Haswell, Pentiums and Celerons have included QSV technology. ; Version 4 (
Broadwell) : The
Broadwell microarchitecture implementation adds VP8 hardware decoding. Also, it has two independent
bit stream decoder (BSD) rings to process video commands on GT3 GPUs; this allows one BSD ring to process decoding and the other BSD ring to process encoding at the same time. ; Version 5 (
Skylake) : The
Skylake microarchitecture implementation adds a full fixed-function
H.265/HEVC 8-bit 4:2:0 decoding and encoding acceleration, hybrid and partial HEVC 10-bit decoding acceleration,
JPEG encoding acceleration for resolutions up to 16,000×16,000 pixels, and partial VP9 decoding and encoding acceleration, although on Linux Intel has explicitly abandoned both the required "hybrid" driver and Skylake accelerated VP9 decoding. ; Version 6 (
Kaby Lake,
Coffee Lake,
Whiskey Lake,
Comet Lake) : The
Kaby Lake,
Coffee Lake,
Whiskey Lake and
Comet Lake microarchitectures implementation adds full fixed-function H.265/HEVC 10-bit 4:2:0 decoding and encoding acceleration, and full fixed-function VP9 8-bit and 10-bit decoding acceleration and 8-bit encoding acceleration. ; Version 7 (
Ice Lake) : The
Ice Lake microarchitecture implementation adds VP9 8-bit and 10-bit decoding and encoding acceleration, H.265/HEVC 8-bit and 10-bit decoding and encoding acceleration with 4:2:2 and 4:4:4 chroma subsampling, and Open Source Media Shaders. HEVC hardware encoding quality has also been improved. ; Version 8 (
Tiger Lake,
Rocket Lake,
Alder Lake,
Raptor Lake) : The
Tiger Lake,
Rocket Lake,
Alder Lake &
Raptor Lake microarchitectures implementation adds VP9 12-bit & 12-bit 4:4:4 hardware decoding and HEVC 12-bit 4:2:0, 4:2:2 and 4:4:4 hardware decoding. Gen12 Xe will also support native AV1 decode, which includes 10-bit 4:2:0 16K stills and 10-bit 4:2:0 8K, 4K and 2K video. Hardware encoding for VP8 was dropped and hardware decoding is only available on Tiger Lake. It removed
VC-1 hardware decoding. ;Version 10 (Intel
Lunar Lake) : Adds
VVC hardware decoding in Xe2 GPU. ==Operating system support==