Latch-up

All CMOS ICs have latch-up paths, but there are several design techniques that reduce susceptibility to latch-up. In CMOS technology, there are a number of intrinsic bipolar junction transistors. In CMOS processes, these transistors can create problems when the combination of n-well/p-well and substrate results in the formation of parasitic n-p-n-p structures. Triggering these thyristor-like devices leads to a shorting of the Vdd and GND lines, usually resulting in destruction of the chip, or a system failure that can only be resolved by power-down. Consider the n-well structure in the first figure. The n-p-n-p structure is formed by the source of the NMOS, the p-substrate, the n-well and the source of the PMOS. A circuit equivalent is also shown. When one of the two bipolar transistors gets forward biased (due to current flowing through the well, or substrate), it feeds the base of the other transistor. This positive feedback increases the current until the circuit fails or burns out. The invention of the now industry-standard technique to prevent CMOS latch-up was made by Hughes Aircraft company in 1977. == Preventing latch-up ==

It is possible to design chips to be resistant to latch-up by adding a layer of insulating oxide (called a trench) that surrounds both the NMOS and the PMOS transistors. This breaks the parasitic silicon-controlled rectifier (SCR) structure between these transistors. Such parts are important in the cases where the proper sequencing of power and signals cannot be guaranteed, such as hot swap devices. Devices fabricated in lightly doped epitaxial layers grown on heavily doped substrates are also less susceptible to latch-up. The heavily doped layer acts as a current sink where excess minority carriers can quickly recombine. Most silicon-on-insulator devices are inherently latch-up-resistant. Latch-up is the low resistance connection between tub and power supply rails. To avoid latchup, a separate substrate tap connection may be placed for each transistor. This reduces the resistance between the current-carrying portions of the substrate and the supply rails, while consuming more wafer area per device. As a compromise, semiconductor fabs may specify design rules for the minimum spacing from a transistor's active area to the nearest substrate tap; for example, 10 μm in a 130 nm technology node. == Testing for latch-up ==

• See EIA/JEDEC STANDARD IC Latch-Up Test EIA/JESD78.This standard is commonly referenced in IC qualification specifications. ==References==