• High Functional Integration on a Single Piece of
Silicon • Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers • Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (USART) • Two Independent Counter/Timers • System Integration Module Incorporates Many Functions Typically Relegated to External PALs, TTL, and ASIC • 32 Address Lines, 16 Data Lines • Power Consumption Control • 0–16.78 MHz or 0–25.16 MHz Operation • 144-Pin Ceramic Quad Flat Pack (CQFP) or 145-Pin Plastic Pin Grid Array (PGA) • Available in 3.3 and 5V ==Family==