MOS Technology 6510

The 6510 and variants were based on the same core as the 6502, and are opcode compatible, including undocumented opcodes. The parallel port was provided by using several formerly unused pins, eliminating some, and re-arranging others. In the original 6502, pins 5, 35 and 36 were not connected. Pin 3, formerly the phase-1 clock out, was eliminated, as most roles did not require it. The 6502 also had two ground pins, on pin 1 and pin 21 on the opposite side of the chip. CLKIN, formerly on pin 37, was moved to pin 1, replacing the redundant ground. SO on pin 38, which was connected to the overflow flag in the processor status register, was eliminated as few applications made use of it and the new parallel port could provide similar functionality. This provided a total of six pins that could be used for the port. To make the layout more practical, the remaining pins were moved. On the left side, two pins were now free, 3 and 5, so all of the pins on that side moved up to fill the gap. This left two pins at the bottom left, so address bus lines 12 and 13, formerly on pins 22 and 23, moved into these positions. Address lines 14 and 15 moved down two spots to fill the gap. CLKIN had moved, SO was removed, and the two unconnected pins on 35 and 26 were free, so the data bus on 33 through 26 moved up four pins. With those pins moving up, and the address lines moving down, there were six free pins in a row, 24 through 29, to be used as the parallel port pins, named P0 through P5. ==Use==

In the C64, the extra I/O pins of the processor are used to control the computer's memory map by bank switching, and for controlling three of the four signal lines of the Datasette tape recorder (the electric motor control, key-press sensing and write data lines; the read data line went to another I/O chip). It is possible, by writing the correct bit pattern to the processor at address $01, to completely expose almost the full 64 KB of RAM in the C64, leaving no ROM or I/O hardware exposed except for the processor I/O port itself and its data directional register at address $00. ==Variants==

MOS 8500 In 1985, MOS produced the 8500, an HMOS version of the 6510. Other than the process modification, it is virtually identical to the NMOS version of the 6510. The 8500 was originally designed for use in the modernised C64, the C64C. However, in 1985, limited quantities of 8500s were found on older NMOS-based C64s. It finally made its official debut in 1987, appearing in a motherboard using the new 85xx HMOS chipset. MOS 7501/8501 The 7501/8501 variant of the 6510 was introduced in 1984. Compared to the 6510, this variant extends the number of I/O port pins from 6 to 8, but omits the pins for non-maskable interrupt and clock output. It is used in Commodore's C16, C116 and Plus/4 home computers, where its I/O port controls not only the Datasette but also the CBM Bus interface. The main difference between 7501 and 8501 CPUs is that they were manufactured with slightly different processes: 7501 was manufactured with HMOS-1 and 8501 with HMOS-2. MOS 8502 The 2 MHz-capable 8502 variant is used in the Commodore 128. MOS 6510T The Commodore 1551 disk drive (for the Commodore Plus/4) uses the 6510T, a version of the 6510 with eight I/O lines. The NMI and RDY signals are not available. ==See also==