Multiplexer

Multiplexers are part of computer systems to select data from a specific source, be it a memory chip or a hardware peripheral. A computer uses multiplexers to control the data and address buses, allowing the processor to select data from multiple data sources. In digital communications, multiplexers allow several connections over a single channel by connecting the multiplexer's single output to the demultiplexer's single input (time-division multiplexing). The image to the right demonstrates this benefit. In this case, the cost of implementing separate channels for each data source is higher than the cost and inconvenience of providing the multiplexing/demultiplexing functions. At the receiving end of the data link, a complementary demultiplexer is usually required to break the single data stream back down into the original streams. In some cases, the far-end system may have functionality greater than a simple demultiplexer, and while the demultiplexing still occurs technically, it may never be implemented discretely. This would be the case when, for instance, a multiplexer serves a number of IP network users; and then feeds directly into a router, which immediately reads the content of the entire link into its routing processor; and then does the demultiplexing in memory from where it will be converted directly into IP sections. Often, a multiplexer and demultiplexer are combined into a single piece of equipment, which is simply referred to as a multiplexer. Both circuit elements are needed at both ends of a transmission link because most communications systems transmit in both directions. In analog circuit design, a multiplexer is a special type of analog switch that connects one signal selected from several inputs to a single output. ==Digital multiplexers==

In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect I_0 to the output, while a logic value of 1 would connect I_1 to the output. In larger multiplexers, the number of selector pins is equal to \left \lceil \log_2(n) \right \rceil where n is the number of inputs. For example, 9 to 16 inputs would require no fewer than 4 selector pins and 17 to 32 inputs would require no fewer than 5 selector pins. The binary value expressed on these selector pins determines the selected input pin. A 2-to-1 multiplexer has a Boolean equation where A and B are the two inputs, S_0 is the selector input, and Z is the output: : Z = ( A \wedge \neg S_0) \vee (B \wedge S_0) or : Z = ( A \cdot \overline{S_0}) + (B \cdot S_0) Which can be expressed as a truth table: Or, in simpler notation: These tables show that when S_0 = 0 then Z = A but when S_0 = 1 then Z = B. A straightforward realization of this 2-to-1 multiplexer would need 2 AND gates, an OR gate, and a NOT gate. While this is mathematically correct, a direct physical implementation would be prone to race conditions that require additional gates to suppress. Larger multiplexers are also common and, as stated above, require \left \lceil \log_2(n) \right \rceil selector pins for n inputs. Other common sizes are 4-to-1, 8-to-1, and 16-to-1. Since digital logic uses binary values, powers of 2 are used (4, 8, 16) to maximally control several inputs for the given number of selector inputs. File:Multiplexer 4-to-1.svg|4-to-1 mux File:Multiplexer 8-to-1.svg|8-to-1 mux File:Multiplexer 16-to-1.svg|16-to-1 mux The Boolean equation for a 4-to-1 multiplexer is: :Z = (A \wedge \neg {S_1} \wedge \neg S_0) \vee (B \wedge \neg S_1 \wedge S_0) \vee (C \wedge S_1 \wedge \neg S_0) \vee (D \wedge S_1 \wedge S_0) or :Z = (A \cdot \overline{S_1} \cdot \overline{S_0}) + (B \cdot \overline{S_1}. S_0) + (C \cdot S_1 \cdot \overline{S_0}) + (D \cdot S_1 \cdot S_0) Which can be expressed as a truth table: The following 4-to-1 multiplexer is constructed from 3-state buffers and AND gates (the AND gates are acting as the decoder): The subscripts on the I_n inputs indicate the decimal value of the binary control inputs at which that input is let through. Chaining multiplexers and mux trees Larger multiplexers can be constructed by using smaller multiplexers by chaining them together in what are called "mux trees". For example, an 8:1 multiplexer can be made with two 4:1 multiplexers and one 2:1 multiplexer. The two 4:1 multiplexer outputs are fed into the 2:1 with the selector pins on the 4:1's put in parallel, giving a total number of selector inputs to 3, which is equivalent to an 8:1. List of ICs which provide multiplexing S54S157 quad 2:1 mux For 7400 series part numbers in the following table, "x" is the logic family. ==Digital demultiplexers==

Demultiplexers take one data input and a number of selection inputs, and they have several outputs. They forward the data input to one of the outputs depending on the values of the selection inputs. Demultiplexers are sometimes convenient for designing general-purpose logic because if the demultiplexer's input is always true, the demultiplexer acts as a binary decoder. This means that any function of the selection bits can be constructed by logically OR-ing the correct set of outputs. If X is the input and S is the selector, and A and B are the outputs: A = ( X \wedge \neg S) B = ( X \wedge S) List of ICs which provide demultiplexing 74F138 1:8 demultiplexer For 7400 series part numbers in the following table, where "x" is the logic family. == Bi-directional multiplexers ==

Bi-directional multiplexers are built using analog switches or transmission gates controlled by the select pins. This allows the roles of input and output to be swapped so that a bi-directional multiplexer can function both as a demultiplexer and a multiplexer. ==Multiplexers as PLDs==

Multiplexers can also be used as programmable logic devices to implement Boolean functions. Any Boolean function of n variables and one result can be implemented with a multiplexer with n selector inputs. The variables are connected to the selector inputs, and the function result, 0 or 1, for each possible combination of selector inputs is connected to the corresponding data input. If one of the variables (for example, D) is also available inverted, a multiplexer with n−1 selector inputs is sufficient; the data inputs are connected to 0, 1, D, or ~D, according to the desired output for each combination of the selector inputs. == Unconventional use of multiplexers for arithmetic ==

Multiplexers have found application in unconventional stochastic computing (SC), particularly in facilitating arithmetic addition. In this paradigm, data is represented as a probability bitstream where the number of '1' bits signifies the magnitude of a value. Thus, the function of a 2-to-1 multiplexer can be conceptualized as a probability function denoted as: y = P(a) \times P(1-s)+P(b)\times P(s) , where a and b are the input bitstream and s is the select input. Using the select input = 0.5 yields: y=\frac{P(a)+P(b)}{2} While this approach doesn't yield exact addition but rather scaled addition, it is deemed acceptable in most SC studies. Multiplexers are extensively utilized for tasks such as average addition, average pooling, and median filtering within SC circuits. Moreover, more sophisticated applications of multiplexers include serving as a Bernstein polynomial function generator, capable of producing arbitrary mathematical functions within the SC domain. Recent research has also revealed that combinations of multiplexers can facilitate large-scale multiply-accumulate operation, demonstrating feasibility in accelerating convolutional neural network on field-programmable gate arrays. ==See also==