Binary counters are widely used as timers and event counters. In a digital timer, the counter is clocked by a periodic digital signal which serves as a time reference and causes the count to change at a constant rate. The clock signal is typically sourced by a stable frequency source such as a
crystal oscillator, either directly or via a clock divider. Depending on the application, a timer may output a signal that indicates timing status, or it may output the current count, or both. In the latter case, the count typically indicates either the elapsed or remaining time. Event counters are typically used to count asynchronous events that may or may not occur at variable frequencies. At any particular time, the current count indicates the number of events that have occurred since event counting began.
Memory addressing Binary counters are used extensively in computers to generate memory addresses. In such applications, the counter output is typically connected to an
address bus and used to sequentially select contiguous memory locations as the count increments or decrements. Widespread examples of this include program counters,
direct memory access (DMA) controllers, and FIFO buffers. When used to hold data addresses during data transfer operations, a counter is commonly referred to as a
memory address register (MAR).
Program counter The
program counter (PC) in a
central processing unit typically consists of a binary counter as shown in the following example: In the above PC, the current count is the
memory address of the next instruction to be executed. Upon processor reset, the count is zeroed so that execution will begin at address zero. When an instruction is fetched from memory, CE (count enable) is asserted to allow the counter to increment the count and thus advance to the next sequential instruction address. If it becomes necessary to switch execution to a different instruction sequence (e.g., due to executing a branch instruction, subroutine call, interrupt, or return from subroutine or interrupt), the address of the first instruction in the new sequence is applied to the Data inputs and Load is asserted; this overrides CE (if asserted) and copies Data to Count.
FIFO Electronic
FIFO (First-In, First-Out) buffers are commonly used to interface data producing devices to data consumers that operate in different clock domains or which, over finite intervals, cannot consume data fast enough to avoid
data loss. The FIFO shown below employs two binary counters as memory address registers (MARs) for a
dual-port RAM. Upon FIFO write, data word WDATA is written to RAM address WADDR and the Write MAR is incremented to prepare for the next write. Upon FIFO read, RDATA receives the data word stored at RAM address RADDR and the Read MAR is incremented. Except for the special case when the FIFO is full, the FIFO level (number of unread words in the FIFO) is equal to WADDR-RADDR. This FIFO may be asynchronous or synchronous, meaning that read and write operations may take place in different clock domains or in a single, common clock domain, respectively. In the latter case, RCLK and WCLK are connected together. In asynchronous FIFOs, the MARs typically output Gray code (vs. binary) to allow them to be safely used for FIFO level detection in both clock domains.
DMA controller Binary counters are used in various ways in direct memory access (DMA) controllers. For example, counters similar to those shown below are utilized when copying a memory buffer via DMA. Two counters are employed as memory address registers (MARs) to generate source and destination addresses for the data to be copied. The MARs are typically bidirectional to allow data transfers to begin at the base or end address of a buffer. A third counter keeps track of the number of remaining words to be transferred. To prepare for the DMA operation, the initial addresses are loaded into the MARs, the buffer size is loaded into the data transfer counter, and the count direction (typically stored in a flip-flop) is programmed for each MAR. When each word transfer completes, CE (count enable) is asserted on all counters, thus causing the MARs to advance to their next address and the remaining word count to decrement. When the remaining count reaches zero, the logic NOR of its bits switches high, thus signaling that the DMA operation has completed.
Timers One-shot timer In digital electronics, a
one-shot timer (or simply
one-shot) is a circuit that produces a single, precisely timed output pulse in response to an input trigger. The digital design allows for easy adjustment of pulse duration and provides high accuracy and repeatability compared to analog counterparts, making digital one-shots preferable for applications where timing accuracy is critical. The one-shot timer shown below uses a binary down-counter to generate an output pulse of precisely controlled duration. The timer output is the logical OR of all bits in the current count, and consequently the output pulse is active while the timer is running (I.e., when the count is not zero). When the count reaches zero, the output pulse is terminated and counting is halted. To start the timer running, a value representing the desired pulse width is applied to the counter's Data inputs and Load is asserted to trigger pulse generation. The pulse width is specified in terms of clock cycles. For example, in the case of a 1 MHz clock, a 100 microsecond output pulse has a duration of 100 clock cycles, as shown below: The one-shot shown above is
retriggerable, meaning that it can be restarted by a subsequent trigger while running and thus stretch (extend the duration of) the output pulse. Conversely, the one-shot shown below is
non-retriggerable, meaning that it will ignore incoming triggers while the output pulse is active.
Periodic interval timer Binary counters are commonly used as
periodic interval timers (PITs), which output periodic pulses at an integer fraction of the clock frequency. PITs are used to generate
system clock interrupts in computers, as clock dividers in phase lock loops and frequency synthesizers, and in many other applications. In the circuit below, a binary down-counter is used to implement a PIT. The interval between output pulses, measured in clock cycles, is stored in the Interval register, resulting in output frequency f_{out} = f_{clock} / (interval + 1). When the count reaches zero, the
NOR gate issues a pulse on the timer output. The output pulse is also used internally to reload the interval into the counter, thus restarting the timer. Each output pulse has a duration of one clock cycle. For example, to obtain a 1 MHz output frequency from a 6 MHz clock, the interval would be set to 5 as shown in the following timing diagram: In applications that require square wave outputs, a PIT is typically used to toggle a flip-flop, resulting in an output frequency equal to half that of the PIT output frequency:
Frequency synthesizer Periodic interval timers are used as clock dividers in
phase-locked loop (PLL)
frequency synthesizers, which generate a precise output frequency by synchronizing a
voltage-controlled oscillator (VCO) to a reference clock. A typical implementation is shown below that outputs frequency f_{out} as a rational multiple of input clock frequency f_{in}. Two clock dividers are used to scale f_{in} and f_{out} by integer divisors M and N, respectively. File:PLL frequency synthesizer.jpg interface clock from a 50 MHz reference When the PLL is in lock, the clock divider outputs have identical frequencies with only a phase difference. An error voltage proportional to the phase difference is generated and used to tune the VCO frequency so as to keep the phase difference small, and thereby maintain an exact N/M ratio between f_{out} and f_{in}.
Pulse width modulator Binary counters are an essential building block in digital
pulse width modulators, which are commonly used to control motor speed, temperature, LED brightness, and other physical processes. These can be implemented in various ways. For example, the pulse width modulator shown below uses a single binary up-counter with synchronous reset to control both the width and frequency of output pulses: The value stored in the PWM period register (Period) determines the output frequency. Count increments at clock frequency f_{clock} until it matches Period, which causes the identity comparator to strobe EndCycle, thus resetting the counter and starting the next output cycle. Consequently, the counter modulus is Period + 1 and the output pulse frequency f_{out} = f_{clock} / (Period + 1). Width specifies the output pulse width in clock periods. The magnitude comparator asserts Preview while Count is less than Width, thus producing a pulse that starts at the beginning of the output cycle and ends when the count reaches Width. A flip-flop buffers Preview to prevent glitches from appearing on the PWM output due to
static hazards. The
duty cycle is the percentage of PWM cycle time in which the pulse is active: Duty cycle = 100 * Width / (Period + 1). For example, the following diagram shows signal timing for Period = 11 and Width = 3, resulting in a 25 percent duty cycle at f_{clock} / 12 Hertz.
Pulse width measurement Pulse width measurement is a common counter application that is used in a wide variety of equipment, including
radar and
sonar,
industrial automation, and
medical imaging systems. A typical circuit is shown below, which uses a binary up-counter to measure the widths of asynchronous (with respect to the counter clock) positive pulses. The measured signal is first synchronized to the counter's clock domain, thus producing the synchronized input signal
Clock gate. This is done to prevent measurement errors due to
metastability or violations of minimum
setup or hold times in the counter and edge detector flip-flops. When a
Clock gate pulse begins, the rising edge detector strobes
Start to zero the count, and the counter then proceeds to count clock pulses while
Clock gate remains active. When the pulse ends, the counter stops counting and the accumulated count indicates the measured pulse width in units of clock periods. The pulse width is Count / f_{clock} seconds, where f_{clock} is the clock frequency in Hertz. A falling edge detector strobes
End to indicate end of measurement, which can be used to signal external circuitry or transfer the count to external storage, or both, before the next measurement begins.
Frequency counter Some counter applications utilize multiple counters. An example of this is the
frequency counter shown below, which uses two counters to measure the frequency of a digital signal. One counter, configured as a one-shot, produces a pulse of precisely controlled width known as the
time gate. The time gate is used to enable the clocking of an event counter, which is clocked by the signal whose frequency is to be measured. When a measurement begins (by asserting
Start), the event counter is zeroed and then proceeds to count rising edges of the unknown frequency signal while the time gate remains active. When the time gate ends, edge counting stops and the accumulated count indicates the measured frequency. The count directly indicates the measured frequency in Hz when the gate time is one second; for other gate times, the count must be scaled to obtain Hz.
Analog-to-digital conversion Counters are employed in various ways in
analog-to-digital converter (ADC) circuits. For example, in a tracking ADC, a bidirectional binary counter is used to control the output voltage (V_{dac}) of a
digital-to-analog converter. V_{dac} is proportional to the count and thus increases or decreases, respectively, when the count is incremented or decremented. A
voltage comparator outputs a bit indicating whether V_{dac} is greater than ADC input voltage V_{in}. This bit controls the count direction such that the count — and DAC voltage — will increase or decrease, respectively, when the V_{dac} is less than or greater than V_{in}, thus causing V_{dac} to track V_{in}. Since the count tracks V_{in} in near real time, it is directly used as ADC output data.
Position tracking Bidirectional binary counters are commonly used to track the physical position of moving objects that are monitored by
incremental encoders, as shown in the example circuit below. A position change is indicated by a rising or falling edge on the encoder's A or B output signal. Each position change is associated with a well-defined distance d, with the phase difference between A and B indicating the direction of travel (e.g., "forward" or "reverse"). The count is incremented or decremented when the object moves in the forward or reverse direction, respectively. To begin tracking, the monitored object is located at a reference position (p_0) and the count is zeroed. From that point on, the count indicates the current position in terms of displacement from the reference position, measured in d distance units: position = p_0 + Count * d. The count is effectively a signed integer in cases where the object can move to either side of the reference position.
Stepped sinusoidal waveform generator A
sinusoidal voltage waveform can be approximated by cycling through the output states of a Johnson counter and
summing the output voltages through a network of resistors which are weighted to map each counter state to a point in the cosine function: The resulting sinusoidal waveform has frequency f_{out} = f_{in}/2n for n flip-flops and a clock frequency of f_{in}. Consequently, the sine wave frequency can be changed simply by changing the clock frequency. Harmonic distortion is reduced by increasing n, which gives more steps and smaller step sizes in the sine wave; by increasing resistance accuracy; and by adding a
capacitor or
active filter to
low-pass filter the edges of voltage steps. == See also ==