The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486. Design work started in June 1989; the team decided to use a
superscalar RISC architecture which would be a convergence of RISC and CISC technology, with on-chip cache, floating-point, and branch prediction.
Vinod Dham then the Vice President of the Microprocessor Product Group and General Manager of Microprocessor Division 5/7 had the concept using this RISC technology into the existing x86 architecture that could compete from the other market. Their performance target could boost FPU by three times and five time over the existing Intel486 CPU. The preliminary design was first successfully simulated in 1990, followed by the
laying-out of the design. By this time, the team had several dozen engineers. It took some 100 million clock cycles of pre-silicon verification test which includes major operating systems and many application were booted and running. They had to use the
Quickturn Systems Inc. software to run pre-silicon simulation program which was 30,000 times quicker than the previous technique method available. By late 1990, they found that the planned feature could not fit into the die, they had to redesign the circuit feature that would slim down in order to fit what the intended design in place without sacrificing the performance. In spring of 1991, the die went another slimming procedure until Dham was happy with the size and its feature without affecting the performance. A group of engineers ran hundreds of tests to validate the designed features and ran 5000 different variables to validate its design. Out of the 14 circuit boards in collection and cables, they only found few bugs using every operating system they have it on hand including in development were used. By February 1992, the design was
taped out in process which was completed by April 1992, at which point beta-testing began. The next few months the design was sent to the Intel's Mask Operation which it translate to mask layout for the
Oregon's Fab 5 to be processed. By mid-1992, the P5 team had 200 engineers. but design problems forced the demo to be cancelled, and the official introduction of the chip was delayed until the spring of 1993. The first computer systems featuring the Pentium appeared in the summer of 1993, the first being
Advanced Logic Research and their Evolution V
workstation, released in the first week of July 1993.
John H. Crawford, chief architect of the original 386, co-managed the design of the P5, along with
Donald Alpert, who managed the architectural team. Dror Avnon managed the design of the FPU.
Vinod K. Dham was general manager of the P5 group. Intel's low-powered
Bonnell microarchitecture employed in early
Atom processor cores also uses an in-order dual pipeline similar to P5. Intel used the Pentium name instead of 586, because in 1991, it had lost a trademark dispute over the "386" trademark, when a judge ruled that the number was
generic. The company hired Lexicon Branding to come up with a new, non-numeric name.
Improvements over the i486 The P5 microarchitecture brings several important advances over the prior i486 architecture. •
Performance: •
Superscalar architecture – The Pentium has two datapaths (pipelines) that allow it to complete two instructions per clock cycle in many cases. The main pipe (U) can handle any instruction, while the other (V) can handle the most common simple instructions. The first instruction goes to the U pipeline, then the next instruction goes to the V pipeline. Both pipelines contain their own
ALU, address generation circuitry and interface to the data cache. Some
reduced instruction set computer (RISC) proponents had argued that the "complicated" x86 instruction set would probably never be implemented by a tightly pipelined
microarchitecture, much less by a dual-pipeline design. The 486 and the Pentium demonstrated that this was indeed possible and feasible. •
64-bit burst-mode external databus doubles the amount of information possible to read or write on each memory access and therefore allows the Pentium to load its code cache faster than the 80486; it also allows faster access and storage of 64-bit and 80-bit
x87 FPU data. Internally, this CPU process the data at 32 bits wide. The external data to the memory is 64 bits wide which doubles the amount of data being transferred in one bus cycle. It includes several types of bus cycles which includes burst mode that loads 256-bit portions of data into its data cache in one bus cycle as well. This data width can transfer data up to 528 Mbytes per second from and to the memory. This rate has increased three-fold over its peak transfer rate of the 50-MHz Intel486 DX CPU. • Separation of code and data in both 8-Kbyte on-chip caches lessens the fetch and operand read/write conflicts compared to the 486. One set is for the instruction, and the other set is for the data. To reduce access time and implementation cost, both of them are
2-way associative, instead of the single 4-way cache of the 486. Using pair of cache's 32-byte lines to match up the 64-bit width with a four-chuck burst length. This cache management conforms to the
MESI cache-consistency protocol. A related enhancement in the Pentium is the ability to read a contiguous block from the code cache even when it is split between two cache lines (at least 17 bytes in worst case). • Much faster
floating-point unit. This component incorporates an eight-stage pipeline that executes at least one floating-point operation every clock cycle. The first four stages of this pipeline use the integer part, and the final four stages are a two-stage floating-point execution, rounding and writing of the result to the register file and the error reporting. This unit also has new algorithms that increase the speed of these common operation by the factor of three time than the predecessor CPU. Some instructions showed an enormous improvement, most notably FMUL, with up to 15 times higher throughput than in the 80486 FPU. The Pentium is also able to execute a FXCH ST(x) instruction in parallel with an ordinary (arithmetical or load/store) FPU instruction. • Four-input address adders enables the Pentium to further reduce the address calculation latency compared to the 80486. The Pentium can calculate full addressing modes with
segment-base +
base-register +
scaled register +
immediate offset in a single cycle; the 486 has a three-input address adder only, and must therefore divide such calculations between two cycles. • The
microcode can employ both pipelines to enable auto-repeating instructions such as REP MOVSW perform one iteration every clock cycle, while the
80486 needed three clocks per iteration (and the earliest x86 chips significantly more than the 486). Also, optimization of the access to the first microcode words during the decode stages helps in making several frequent instructions execute significantly more quickly, especially in their most common forms and in typical cases. Some examples are (486→Pentium, in clock cycles): CALL (3→1), RET (5→2), shifts/rotates (2–3→1). • A faster, fully hardware-based multiplier makes instructions such as MUL and IMUL several times faster (and more predictable) than in the 80486; the execution time is reduced from 13 to 42 clock cycles down to 10–11 for 32-bit operands. • Virtualized interrupt to speed up
virtual 8086 mode. • Dynamic Branch Prediction using the
branch target buffer method that contains a small cache block. Using the
Sieve of Eratosthenes benchmark method requires six clock cycles to execute on the Intel486 CPU down to two clock cycles in this CPU. •
Other features: • Enhanced debug features with the introduction of the Processor-based debug port (see
Pentium Processor Debugging in the Developers Manual, Vol 1). • Enhanced self-test features like the L1 cache parity check (see
Cache Structure in the Developers Manual, Vol 1). Other built-in features include an
IEEE 1149.1 compliant access architecture for testing external connectivity to the CPU and a probe mode to access the software visible register and the processor state. • New instructions: CPUID, CMPXCHG8B, RDTSC, RDMSR, WRMSR, RSM. • Test registers TR0–TR7 and MOV instructions for access to them were eliminated. • The later Pentium MMX also added the
MMX instruction set, a basic integer
single instruction, multiple data (
SIMD) instruction set extension marketed for use in
multimedia applications. MMX could not be used simultaneously with the
x87 FPU instructions because the registers were reused (to allow fast context switches). More important enhancements were the doubling of the instruction and data cache sizes and a few microarchitectural changes for better performance. The Pentium was designed to execute over 100 million
instructions per second (MIPS), and the 75 MHz model was able to reach 126.5 MIPS in certain benchmarks. The Pentium architecture typically offered just under twice the performance of a 486 processor per clock cycle in common benchmarks. The fastest 80486 parts (with slightly improved microarchitecture and 100 MHz operation) were almost as powerful as the first-generation Pentiums, and the
AMD Am5x86, which despite its name is actually a 486-class CPU, was roughly equal to the Pentium 75 regarding pure ALU performance.
Errata The early versions of 60–66 MHz P5 Pentiums had a problem in the floating-point unit that resulted in incorrect (but predictable) results from some division operations. This flaw, discovered in 1994 by professor Thomas Nicely at Lynchburg College, Virginia, became widely known as the
Pentium FDIV bug and caused embarrassment for Intel, which created an exchange program to replace the faulty processors. In 1997, another erratum was discovered that could allow a malicious program to crash a system without any special privileges, the "
F00F bug". All P5 series processors were affected, and no fixed steppings were ever released. However, contemporary operating systems were patched with workarounds to prevent crashes. ==Cores and steppings==