Sunny Cove (microarchitecture)

Sunny Cove was designed by Intel Israel's processor design team in Haifa, Israel. Intel released details of Ice Lake and its microarchitecture, Sunny Cove, during Intel Architecture Day in December 2018, stating that the Sunny Cove cores would be focusing on single-thread performance, new instructions, and scalability improvements. Intel stated that the performance improvements would be achieved by making the core "deeper, wider, and smarter". Sunny Cove features a 50% increase in the size of L1 data cache, a larger L2 cache dependent on product size, larger μOP cache, and larger second-level TLB. The core has also increased in width, by increasing execution ports from eight to ten and by doubling the L1 store bandwidth. Allocation width has also increased from four to five. The 5-level paging scheme supports a linear address space up to 57 bits and a physical address space up to 52 bits, increasing the virtual memory space to 128 petabytes, up from 256 terabytes, and the addressable physical memory to 4 petabytes, up from 64 terabytes. • Increase L1 data cache: 48 kiB (from 32 kiB) • L2 cache: 512 kiB • Larger micro-instruction cache (2304 entries, up from 1536) • Larger re-order buffer (352, up from 224 entries) • Dynamic Tuning 2.0 which allows the CPU to stay at turbo frequencies for longer • Hardware acceleration for SHA operations (Secure Hash Algorithms) • New AVX-512 instruction subsets: • VPOPCNTDQ • VBMI2 • BITALG • VPCLMULQDQ • GFNI • VAES • VNNI • Wider decoder (from skylake's 3 simple + 1 complex 4 way decoding to Sunny cove's 4 simple + 1 complex 5 wide decoder) • 1.6x larger ROB (352, up from 224 entries) • Scheduler • 1.65x larger scheduler (160-entry, up from 97 entries) • Larger dispatch (10-way, up from 8-way) • 1.55x larger integer register file (280-entry, up from 180) • 1.33x larger vector register file (224-entry, up from 168) • Distributed scheduling queues (4 scheduling queues, up from 2) • Intel Deep Learning Boost, used for machine learning/artificial intelligence inference acceleration == Cypress Cove ==

Cypress Cove is a CPU microarchitecture based on the Sunny Cove microarchitecture designed for 10 nm, backported to 14 nm. It succeeds the Skylake microarchitecture, and is manufactured using Intel's 14 nm process node. Cypress Cove is identical to Sunny Cove, aside from a number of improvements and other changes. Notably the L1 data cache latency has been reduced from five cycles that is on Sunny Cove to just three cycles on Cypress Cove by change from 8 way associativity on Sunny Cove to 12 way associativity On Cypress Cove. Intel claims an increase of 19% in IPC in Cypress Cove–based Rocket Lake processors compared to Comet Lake. Cypress Cove is implemented on 11th Gen Intel Core desktop processors (codenamed Rocket Lake). Rocket Lake and its underlying microarchitecture were first described in November 2020, and was later released on March 30, 2021. SGX is removed from Rocket Lake. == Products ==

Sunny Cove powers the 10th generation of Intel Core mobile processors (codenamed Ice Lake) and the third generation of Xeon Scalable server processors (codenamed Ice Lake-SP). Cypress Cove is implemented on 11th-generation Intel Core desktop processors (codenamed Rocket Lake). == References ==