The PIO interface is grouped into different modes that correspond to different
transfer rates. The
electrical signaling among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance. The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually
Ultra Direct Memory Access (UDMA) interface was created to increase performance. The simple digital logic needed to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are unneeded as in
embedded systems, or with
field-programmable gate array (FPGA) chips, where PIO mode can be used with no significant performance loss. Two additional advanced timing modes have been defined in the
CompactFlash specification 2.0. Those are PIO modes 5 and 6. They are specific to CompactFlash.
PIO Mode 5 A PIO Mode 5 was proposed with operation at 22 MB/s, but was never implemented on hard disks because CPUs of the time would have been severely slowed waiting for the hard disk at the proposed PIO 5 timings, and the
DMA standard ultimately obviated it. While no
hard disk drive was ever manufactured to support this mode, some
motherboard manufacturers preemptively provided
BIOS support for it. PIO Mode 5 can be used with CompactFlash cards connected to ATA via CF-to-ATA adapters. == See also ==