Registered memory

Normally, there is a performance penalty for using registered memory. Each read or write is buffered for one cycle between the memory bus and the DRAM, so the registered RAM can be thought of as running one clock cycle behind the equivalent unregistered DRAM. With SDRAM, this only applies to the first cycle of a burst. However, this performance penalty is not universal. There are many other factors involved in memory access speed. For example, the Intel Westmere 5600 series of processors access memory using interleaving, wherein memory access is distributed across three channels. If two memory DIMMs are used per channel, there is a reduction of maximum memory bandwidth for this configuration with UDIMM by some 5% in comparison to RDIMM. ==Compatibility==

Usually, the motherboard must match the memory type; as a result, registered memory will not work in a motherboard not designed for it, and vice versa. Some PC motherboards accept or require registered memory, but registered and unregistered memory modules cannot be mixed. There is much confusion between registered and ECC memory; it is widely thought that ECC memory (which may or may not be registered) will not work at all in a motherboard without ECC support, not even without providing the ECC functionality, although the compatibility issues actually arise when trying to use registered memory (which often supports ECC and is described as ECC RAM) in a PC motherboard that does not support it. == Buffered memory types ==

Clocked Unbuffered DIMM (') and Clocked Small Outline DIMM () modules include a buffer on the clock bus, but are otherwise unbuffered. This enhances clock integrity at higher speeds at relatively little added cost. They were introduced for DDR5 in 2024. The clock buffer is also called a client clock driver' (CKD). Systems that do not support CUDIMM/CSODIMM can still use them after a BIOS update that allows for using the modules in pass-through mode. , as a result of one additional clock cycle required for the address to traverse the additional buffer. Early registered RAM modules were physically incompatible with unregistered RAM modules, but the two variants of SDRAM R-DIMMs are mechanically interchangeable, and some motherboards may support both types. Load Reduced DIMM (LR-DIMM or LRDIMM) modules are similar to R-DIMMs, but add a buffer to the data lines as well. In other words, LR-DIMMs buffer both control and data lines while keeping the parallel nature of all signals. As a result, LR-DIMMs provide large overall maximum memory capacities, while avoiding the performance and power consumption problems of FB-DIMMs, induced by the required conversion between serial and parallel signal forms. Fully Buffered DIMM (FB-DIMM) modules increase maximum memory capacities in large systems even more, using a more complex buffer chip to translate between the wide bus of standard SDRAM chips and a narrow, high-speed serial memory bus. In other words, all control, address and data transfers to FB-DIMMs are performed in a serial fashion, while the additional logic present on each FB-DIMM transforms serial inputs into parallel signals required to drive memory chips. By reducing the number of pins required per memory bus, CPUs could support more memory buses, allowing higher total memory bandwidth and capacity. Unfortunately, the translation further increased memory latency, and the complex high-speed buffer chips used significant power and generated a lot of heat. Both FB-DIMMs and LR-DIMMs are designed primarily to minimize the load that a memory module presents to the memory bus. They are not compatible with R-DIMMs, and motherboards that require them usually will not allow mixing types of memory modules. == References ==