Rigel (microprocessor)

The Rigel architecture was based on the VAX 8800 processor. It has a six-stage microinstruction pipeline and 64-entry fully associative translation look-aside buffer. The Rigel chip set supported an optional vector processor and the REX520 decoded any vector instructions and passed on to the vector interface (VC) chip by the REX520. The REX520 has a 2 KB unified primary cache, configurable as an instruction cache and an external 128 KB secondary cache (backup cache) implemented with CMOS static random access memory (SRAM) chips. The REX520 has an external cache because the VAX 8800's 64 KB primary cache could not be integrated on the same die. The backup cache controller was located on the VC chip. The REX520 consisted of 320,000 transistors, of which 140,000 are for logic and 180,000 for memory. The die measures 12 mm by 12 mm (144 mm²). It was packaged in a 224-lead ceramic leaded package. == Fabrication ==

The chip set was fabricated by DEC in their second-generation complementary metal–oxide–semiconductor (CMOS) process, CMOS-2. The process had a 1.5 μm minimum feature size and two levels of aluminium interconnect. == Mariah ==

Mariah was a revised version of the Rigel chip set fabricated by DEC in their 1 μm CMOS-3 process, with higher clock frequencies between 55 and 71 MHz. The Mariah CPU, FPU and cache controller were designated DC595, DC596 and DC597 respectively. Enhancements over Rigel included a 4 kB first-level cache and 32-bit physical memory addressing in the Mariah CPU, and write-back caching implemented in the cache controller chip. Mariah was used in the VAX 6000 Model 500, MicroVAX 3100 Model 80 and VAXstation 4000 Model 60. == References ==