CPU Sigma systems provided a range of performance, roughly doubling from Sigma 5, the slowest, to Sigma 9 Model 3, the fastest. For example, 32-bit fixed point multiply times ranged from 7.2 to 3.8 μs; 64-bit floating point divide ranged from 30.5 to 17.4 μs. Most Sigma systems included two or more blocks of 16 general-purpose registers. Switching blocks is accomplished by a single instruction (LPSD), providing fast context switching, since registers do not have to be saved and restored.
Memory Memory in the Sigma systems can be addressed as individual bytes, halfwords, words, or doublewords. All 32-bit Sigma systems except the Sigma 5 and Sigma 8 used a
memory map to implement
virtual memory. The following description applies to the Sigma 9, other models have minor differences. The
effective virtual address of a word is 17 bits wide. Virtual addresses 0 thru 15 are reserved to reference the corresponding general purpose register, and are not mapped. Otherwise, in virtual memory mode the high-order eight bits of an address, called
virtual page number, are used as an index to an array of 256 13-bit memory map registers. The thirteen bits from the map register plus the remaining nine bits of the virtual address form the address used to access real memory. Access protection is implemented using a separate array of 256 two-bit access control codes, one per virtual page (512 words), indicating a combination of read/write/execute or no access to that page. Independently, an array of 256 2-bit
access control registers for the first 128k words of
real memory function as a "lock-and-key" system in conjunction with two bits in the program status doubleword. The system allows pages to be marked "unlocked", or the key to be a "master key". Otherwise the key in the PSD had to match the lock in the access register in order to reference the memory page.
Diagnostic facilities All the frames were powered by a PT16B power supply which took HF power input from a PT14/PT15 pair mounted on the rear frame rack. The PT16s could be margined by a switch to increase or decrease voltages (+4, +8 and -4) by 5% in order to amplify failing components. The control panel also had a switch to allow increasing or decreasing basic
clock rate for the same reason. These were for use by maintenance staff. The Sigma 9 also had a series of registers called "SNAP" registers. The collected the status of various internal registers in the system at each clock tick. The major CPU diagnostics, for example 9Auto, 9Suffix) which tested various instructions, were supplied with a
9-track tape containing "Snap Data". This allowed the diagnostic, on an error detection, to run the instruction in "Snap Mode" which allowed the system to repeat the instruction one CPU phase at a time and collect the real data in the snap registers and compare it with correct example snap data from the snap tape. In this way an engineer could quickly see where a register bit was failing, amongst some other failure types.
Peripherals Input/output is accomplished using a
control unit called an
IOP (Input-output processor). An IOP provides an 8-bit data path to and from memory. Systems support up to 8 IOPs, each of which can attach up to 32 device controllers. An IOP can be either a
selector I/O processor (SIOP) or a
multiplexer I/O processor (MIOP). The SIOP provides a data rate up to 1.5 megabytes per second (MBPS), but allows only one device to be active at a time. The MIOP, intended to support slow speed peripherals allows up to 32 devices to be active at any time, but provides only a .3 MBPS aggregate data rate.
Mass storage The primary
mass storage device, known as a RAD (
random-access disk), contains 512 fixed heads and a large (approx 600 mm/24 in diameter) vertically mounted disk spinning at relatively low speeds. Because of the fixed head arrangement, access is quite fast. Capacities range from 1.6 to 6.0 megabytes and are used for temporary storage. Large-capacity multi-platter disks are employed for permanent storage.
Communications The Sigma 7611
Character Oriented Communications subsystem (
COC) supports one to seven
Line Interface Units (LIUs). Each LIU can have one to eight line interfaces capable of operating in
simplex,
half-duplex, or
full-duplex mode. The COC was "intended for low to medium speed character oriented data transmissions." The optional Communication Input/Output Processor or CIOP handled up to 128 communication lines at speeds from 128 to 9600 baud. It used 1K of dedicated mainframe memory for control and line status.
System control unit The
System Control Unit (SCU) was a "
microprogrammable data processor" which can interface to a Sigma CPU, and "to peripheral and
analog devices, and to many kinds of line protocol." The SCU executes horizontal microinstructions with a 32-bit word length. A
cross-assembler running on a Sigma system can be used to create microprograms for the SCU.
Carnegie Mellon Sigma 5 The Sigma 5 computer owned by
Carnegie Mellon University was donated to the
Computer History Museum in 2002. The system consists of five full-size cabinets with a monitor, control panel and a printer. It is possibly the last surviving Sigma 5 that is still operational. The Sigma 5 sold for US$300,000 with 16
kilowords of random-access
magnetic-core memory, with an optional memory upgrade to 32 kW for an additional $50,000. The
hard disk drive had a capacity of 3
megabytes. == 32-bit software ==