The SSE5 specification included a proposed extension to the general coding scheme of
x86 instructions in order to allow instructions to have more than two operands. In 2008,
Intel announced their planned
AVX instruction set which proposed a different way of coding instructions with more than two operands. The two proposed coding schemes, SSE5 and AVX, are mutually incompatible, although the AVX scheme has certain advantages over the SSE5 scheme: most importantly, AVX has plenty of space for future extensions, including larger vector sizes. In May 2009, AMD published a revised specification for the planned future instructions. This revision changes the coding scheme to make it compatible with the AVX scheme, but with a differing prefix byte in order to avoid overlap between instructions introduced by AMD and instructions introduced by Intel. The revised instruction set no longer carries the name SSE5, which has been criticized for being misleading, but most of the instructions in the new revision are functionally identical to the original SSE5 specification—only the way the instructions are coded differs. The planned additions to the AMD instruction set consists of three subsets: •
XOP: Integer vector
multiply–accumulate instructions, integer vector horizontal addition, integer vector compare, shift and rotate instructions, byte permutation and conditional move instructions, floating point fraction extraction. •
FMA4: Floating-point vector
multiply–accumulate. •
F16C:
Half-precision floating-point conversion. Both XOP and FMA4 are removed in newer AMD processors using the
Zen microarchitecture. ==See also==