The half subtractors can be designed through the combinational Boolean logic circuits [2] as shown in Figure 1 and 2. The half subtractor is a
combinational circuit which is used to perform subtraction of two bits. It has two inputs, the
minuend X and
subtrahend Y and two outputs the difference D and borrow out B_\text{out}. The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is, B_{\text{out}} = 1 when X . Since X and Y are bits, B_\text{out} = 1 if and only if X = 0 and Y = 1. An important point worth mentioning is that the half subtractor diagram aside implements X - Y and not Y-X since B_\text{out} on the diagram is given by :B_{\text{out}} = \overline{X} \cdot Y. This is an important distinction to make since subtraction itself is not
commutative, but the difference bit D is calculated using an
XOR gate which is commutative. The
truth table for the half subtractor is: Using the table above and a
Karnaugh map, we find the following logic equations for D and B_\text{out}: :D = X \oplus Y :B_\text{out} = \overline X \cdot Y. Consequently, a simplified half-subtract circuit, advantageously avoiding crossed traces in particular as well as a negate gate is: X ── XOR ─┬─────── |X-Y|, is 0 if X equals Y, 1 otherwise ┌──┘ └──┐ Y ─┴─────── AND ── borrow, is 1 if Y > X, 0 otherwise where lines to the right are outputs and others (from the top, bottom or left) are inputs. ==Full subtractor==