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System Management Bus

The System Management Bus is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in chipsets of computer motherboards for communication with the power source for ON/OFF instructions. The exact functionality and hardware interfaces vary with vendors.

SMBus/I²C Interoperability
While SMBus is derived from I²C, there are several major differences between the specifications of the two busses in the areas of electricals, timing, protocols and operating modes. Electrical Input Voltage (VIL and VIH) When mixing devices, the I²C specification defines the input levels to be 30% and 70% of the supply voltage VDD, which may be 5 V, 3.3 V, or any other value. Instead of relating the bus input levels to VDD, SMBus defines them to be fixed. SMBus 2.0 defines VIL,max at 0.8 V and VIH,min at 2.1 V, and supports a VDD ranging from 3 to 5 V, while in SMBus 3.0, the levels are defined at 0.8 and 1.35 V, with a VDD ranging from 1.8 to 5 V. SMBALERT# The SMBus has an extra optional shared interrupt signal called SMBALERT#, which can be used by slaves to tell the host to ask its slaves about events of interest. SMBus also defines a less common "Host Notify Protocol", providing similar notifications but passing more data and building on the I²C multi-master mode. ==Support==
Support
SMBus devices are supported by FreeBSD, OpenBSD, NetBSD, DragonFly BSD, Linux, Windows 98 and newer and Windows CE. == Replacement ==
Replacement
DDR5 introduces I3C for its presence detect communication, replacing SMBus. PCI express devices commonly use SMBus as a "out-of-band management port". However, device vendors frequently use SMBus multiplexers (Mux) to manage address clashes (which are in turn caused by them not implementing the Address Resolution Protocol), causing link interruptions that break Management Component Transport Protocol and other protocols when the Mux switches targets. To solve this problem, SNIA's Enterprise and Data Center Standard Form Factor version 3.1 (January 2023) describes a way to use I3C basic over the PCIe two-wire interface. NVM Express 2.1 (August 2024) is also reworded to allow the use of I3C, "to match the new conventions used by SNIA SFF TA's EDSFF and PCI-SIG specifications for I3C". == See also ==
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