The T2 is a commodity derivative of the
UltraSPARC series of microprocessors, targeting Internet workloads in computers, storage and networking devices. The processor, manufactured in
65 nm, is available with eight CPU cores, and each core is able to handle eight
threads concurrently. Thus the processor is capable of processing up to 64 concurrent threads. Other new features include: • Speed bump for each thread, which increased the frequency from 1.2
GHz to 1.6 GHz • One
PCI Express port (x8 1.0) vs. the T1's
JBus interface • Two
Sun Neptune 10 Gigabit Ethernet ports (embedded into the T2 processor) with packet classification and filtering •
L2 cache size increased to 4 MB (8-banks, 16-way associative) from 3 MB • Improved thread scheduling and instruction prefetching to achieve higher single-threaded performance • Two integer
ALUs per core instead of one, each one being shared by a group of four threads • One
floating point unit per core, up from just one
FPU for the entire
chip • Eight encryption engines, with each supporting
DES,
Triple DES,
AES,
RC4,
SHA1,
SHA256,
MD5,
RSA-2048,
ECC,
CRC-32 • Hardware random number generator • Four dual-channel
FBDIMM memory controllers ==Core pipeline==