VAX 9000

DEC in the 1980s As the 1980s opened, DEC had been moving from strength to strength. The PDP-11 was released in 1970 and continued strong sales that would ultimately reach 600,000 machines, while their newly introduced VAX-11 picked up where the PDP ended and was beginning to make major inroads to IBM's midrange market. DEC also introduced their famous VT series computer terminals and a wide variety of other popular peripherals that all generated significant cashflow. Through this period, DEC made several attempts to enter the personal computer field, but these all failed. Best known among these was the Rainbow 100, which aimed to offer the ability to run both MS-DOS and CP/M programs, but instead demonstrated itself incapable of doing either very well while costing about as much as buying two separate machines. As the PC market expanded, DEC abandoned their PC offerings and increasingly turned their attention to the midrange market. As part of this change in focus, a number of longstanding policies were changed, causing friction with their customer base, and especially with their third-party developers. In one example, their new VAXBI Bus could not be used by other developers unless they signed a development agreement. This was a stark contrast to the Unibus standard of the PDP and earlier VAX machines, which had a thriving market of 3rd party products. Ken Olsen was quoted as saying "We spent millions developing this bus. I don't know why we didn't do it before." As these policies were "closing" DEC, new companies were quick to take advantage of this. Notable among these was Sun Microsystems, whose Motorola 68000-based systems offered performance similar to DEC's VAXstation series while being based on the UNIX operating system. During the second half of the 1980s, Sun increasingly pitched itself as the replacement for DEC in the technical market, branding DEC as a closed, proprietary "bloodsucker". This was aided by DEC's own 1985 decision to abandon the technical market in favor of the higher margins in the data center. ECL During the 1960s, DEC computers had been built out of individual transistors and began to move to using small scale integration integrated circuits (SSI ICs). These would be built onto a number of circuit boards, which would then be wire wrapped together on a backplane to produce the central processing unit (CPU). As semiconductor manufacturing ("fab") improved, the machines could be reimplemented using a smaller number of chips. By the late 1970s, LSI versions of the PDP-11 were available, first as multi-chip units like DEC's own LSI-11, and later in single-chip versions like the J-11. The same evolution began to appear in the VAX line as well. Early VAX models resembled the PDP's of the earlier generations, but with multiple LSI chips on printed circuit boards building up the more complex CPU rather than SSI chips on wire-wrapped boards. By the mid-1980s, the relentless effects of Moore's law had pushed LSI into what was now very large scale integration (VLSI), and single-chip versions of the VAX began to appear, like late 1987's single-chip CVAX. DEC was facing the possibility that some future VAX machine would sit on a desktop and sell for a fraction of the cost of their current machines. If they didn't build such a system, someone else would. Looking for options that would maintain their margins, the company began to consider high-performance system that could not be implemented in current CMOS form. One possibility would be to make a machine using the faster emitter-coupled logic (ECL). ECL's density was lower, and its feature sizes were about a generation behind CMOS. This meant that the machine would require a much larger number of individual chips, along with a huge number of inter-chip connections. The inter-chip wiring proliferation was proportional to the massive pin count increase required by modern machines’ address space growth. In 1980, Gene Amdahl formed Trilogy Systems to solve problems in high-performance ECL-based mainframe production. Trilogy's developments included a new inter-chip connection system using copper conductors embedded in polyimide insulation to produce a thin-film with extremely dense wiring. In 1984, DEC licensed parts of Trilogy's technologies and began development of practical versions of these concepts at their Hudson Fab. This was the birth of the 9000 project. In contrast to Trilogy's goal of introducing their own plug-compatible mainframes and competing with IBM directly, believing it worked on trivial five-line programs but would not be successful in the transaction processing field. This opinion was turned upside down in 1986 when an experimental RISC developed at DEC's Western Research Lab was compared head-to-head with the latest VAX 8800 and outperformed it 2-to-1. This led to a program to develop a production-quality scalable RISC design, which emerged as the DEC PRISM. Dave Cutler, in charge of the PRISM design, then began to develop a high-end machine using it, immediately leading to fighting with the Aridus group who saw them as stepping on "their turf." The company's engineering committee, the Strategy Task Force, repeatedly advised cancelling Aridus. Every year they would attempt to cut the budget for the project, only to have the project lead, Bob Glorioso, go directly to Ken Olsen and the board and have it reinstated, saying "these engineers have no right to tell us business people what to do." While the battle between the RISC and ECL groups continued, the CMOS team building VAX processors was continuing to improve as well. Bob Supnik claims that it was clear to senior technical people as early as 1987 that the next generation of CMOS chips, the NVAX, would perform as well as the 9000 by 1988, even though the 9000 was not slated to launch until 1989. There are several quotes by prominent engineers on the NVAX project that describe Olsen's unwillingness to kill the 9000 even after being told point-blank that it would not be competitive by the early 1990s, and his outright rejection that such a thing was even possible. As the company continued to back the 9000 while it became more and more clear it would not be competitive, various groups within the company began developing RISC-based systems. The unlikely outcome of this was that all of the RISC projects were instead killed off with the exception of some ongoing work at the Hudson Fab on a low-end PRISM. Release DEC formally announced the 9000's in October 1989, claiming at the time that it would ship "next spring." Comparing it to a low-end IBM 3090, IBM's flagship mainframe, DEC positioned the machine for transaction processing and high-end database systems. Five systems were announced, from $1.2 to $3.9 million, spanning a performance range from 30 to 117 times that of the 11/780. The development of the 9000 eventually ran to about $3 billion. Slated for release in 1989, delays in the chip manufacturing delayed it by a year, and further delays in building the complete machine meant only tiny numbers were delivered in 1990. The systems were plagued with problems and required constant maintenance in the field. By 1991 the company had an order book of only 350 systems. At $1.5 million per machine, the system had recouped only 25% of the development costs, excluding actual manufacturing. In February 1991, they announced a low-end version, the Model 110 at $920,000, appealing to customers looking for CPU power without the need for extensive storage or other options. Meanwhile, the engineering team's predictions about the relentless march of CMOS proved true. By 1991, the NVAX was also on the market, offering roughly the same performance for a tiny fraction of the cost and size. At lower performance settings the same design was available in desktop form, outperforming all previous VAX machines. The 9000 managed not only to lose billions of dollars, but also led to the ending of several much more promising designs. Refocus By 1991, industry observers were describing the 9000 as "stalled" and "disappointing". In August, Glorisoso left DEC, claiming family issues. In October 1991, DEC announced that the division would be reorganized as the Production System Business Unit, along with cuts on the prices of the current 9000 models of 30%, and 38% on its server software. They also announced three new models based on CMOS chips, the 9X15, 9600 and 9800, none of which shipped. They also announced that existing users of the 9000 would be offered a discounted upgrade path to new DEC Alpha-based systems. Adding to the woes, in early 1992 it was reported that installed systems had begun to suffer a series of hardware failures that appeared to start in the second half of 1991. A study suggested 37% of the installed systems suffered "hard failure", mostly on the 9420 models. A follow-up survey gave the system high marks for service and compatibility with other DEC systems, but low marks for reliability and cost. == Description ==

The VAX 9000 was a multiprocessor and supported one, two, three or four CPUs clocked at 62.5 MHz (16 ns cycle time). The system was based around a crossbar switch in the system control unit (SCU), to which the one to four CPUs, two memory controllers, two input/output (I/O) controllers and a service processor connected. I/O was provided by four Extended Memory Interconnect (XMI) buses. Scalar processor Each CPU was implemented with 13 Multi-Chip Units (MCUs), with each MCU containing several emitter-coupled logic (ECL) macrocell arrays which contained the CPU logic. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a bipolar process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by in size. Vector processor The VAX 9000's CPU was coupled with a vector processor with a maximum theoretical performance of 125 MFLOPS. The vector processor circuitry was present in all units shipped and disabled via a software switch on units sold 'without' the vector processor. The vector processor was referred to as the V-box, and it was Digital's first ECL implementation of the VAX Vector Architecture. The design of the vector processor began in 1986, two years after development of the VAX 9000 CPU had begun. The V-box implementation comprised 25 Motorola Macrocell Array III (MCA3) devices spread over three multichip units (MCUs), which resided on the planar module. The V-box consisted of six subunits: the vector register unit, the vector add unit, vector multiply unit, vector mask unit, vector address unit and the vector control unit. The vector register unit, also known as the vector register file, implemented the 16 vector registers defined by the VAX vector architecture. The vector register file was multi-ported and contained three write ports and five read ports. Each register consisted of 64 elements, and each element was 72 bits wide, with 64 bits used to store data and 8 bits used to store parity information. SID Scalar and Vector Processor Synthesis SID (Synthesis of Integral Design) was a logic synthesis program used to generate logic gates for the VAX 9000. From high-level behavioral and register-transfer level sources, approximately 93% of the CPU scalar and vector units, over 700,000 gates, were synthesized. SID was an artificial intelligence rule-based system and expert system with over 1000 hand-written rules. In addition to logic gate creation, SID took the design to the wiring level, allocating loads to nets and providing parameters for place and route CAD tools. As the program ran, it generated and expanded its own rule-base to 384,000 low-level rules. A complete synthesis run for the VAX 9000 took 3 hours. SID’s artificial intelligence software could produce designs superior to those of any one expert logic designer. It could base decisions on a wide range of parameters, for example, size and timing. A logic designer expert at making high performance designs would input rules to make the resulting computer design fast. Another designer expert at making compact designs would input rules for minimum size. Another designer expert on circuit loading and path distance wiring would input still other rules. Through iterations of conflicting rules, SID would produce the superior design. The program would run complete passes through the entire logic design, repeating the full run, each time with fewer rules firing, until it reached a state of equilibrium. SID was the first artificial intelligence program capable of self-modification and self-learning, i.e., it could create its own rules from other rules input by design experts. Initially it was somewhat controversial but was accepted in order to reduce the overall VAX 9000 project budget. Some engineers refused to use it. Others compared their own gate-level designs to those created by SID, eventually accepting SID for the gate-level design job. Since SID rules were written by expert logic designers and with input from the best designers on the team, excellent results were achieved. As the project progressed and new rules were written, SID-generated results became equal to or better than manual results for both area and timing. For example, SID produced a 64-bit adder that was faster than the manually-designed one. Manually-designed areas averaged 1 bug per 200 gates, whereas SID-generated logic averaged 1 bug per 20,000 gates. After finding a bug, SID rules were corrected, resulting in 0 bugs on subsequent runs. The SID-generated portion of the VAX 9000 was completed 2 years ahead of schedule, whereas other areas of the VAX 9000 development encountered implementation problems, resulting in a much delayed product release. Following the VAX 9000, SID was never used again. == Models ==

VAX 9000 Model 110 The VAX 9000 Model 110 was an entry-level model with the same performance as the Model 210 but had a smaller memory capacity and was bundled with less software and services. On 22 February 1991, it was priced from US$920,000, and if fitted with a vector processor, from US$997,000. VAX 9000 Model 210 The VAX 9000 Model 210 was an entry-level model with one CPU that could be upgraded. If a vector processor was present, it was known as the VAX 9000 Model 210VP. VAX 9000 Model 4x0 The VAX 9000 Model 4x0 was a multiprocessor capable model, the value of "x" (1, 2, 3 or 4) denoting the number of CPUs present. These models supported the vector processor, with one vector processor supported per CPU. A maximal configuration had 512 MB of memory. The number of I/O buses supported varied, with the Model 410 and 420 supporting two XMI, ten CI and eight VAXBI; while the Model 430 and 440 supported four XMI, ten CI and 14 VAXBI. ==Notes==