The N version datasheet has a note regarding the Transmitter Data Register Empty flag: "The W65C51N loads the Transmitter Data Register (TDR) and Transmitter Shift Register (TSR) at the same time. A delay should be used to insure that the
shift register is empty before the TDR/TSR is reloaded. This feature of the W65C51N works different from earlier 6551 designs." This means the TDRE flag cannot be relied on for flow control. It has been reported that some W65C51 chips have the TDRE flag stuck high ==References==