3 nm process

Research and technology demos In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes. In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology. Commercialization history In late 2016, TSMC announced plans to construct a "5 nm"–"3 nm" node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion. In 2017, TSMC announced it was to begin construction of the "3 nm" semiconductor fabrication plant at the Tainan Science Park in Taiwan. TSMC plans to start volume production of the "3 nm" process node in 2023. In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out "3 nm" test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography. In early 2019, Samsung presented plans to manufacture "3 nm" GAAFET (gate-all-around field-effect transistors) at the "3 nm" node in 2021, using its own MBCFET transistor structure that uses nanosheets; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with "7 nm". Samsung's semiconductor roadmap also included products at "8", "7", "6", "5", and "4 nm" nodes. In December 2019, Intel announced plans for "3 nm" production in 2025. In January 2020, Samsung announced the production of the world's first "3 nm" GAAFET process prototype, and said at that time that it was to have imminently been targeting mass production in 2021. In August 2020, TSMC announced details of its "N3" process, which was new rather than being an improvement over its "N5" process. Compared with the "N5" process, the "N3" process was at that point in time projected to have been offering a 10–15% increase in performance, or a 25–35% decrease in power consumption, with a 70% increase in logic density, a 20% increase in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs included considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks were at that point expected to have only been of around 26%. TSMC was planning volume production in the second half of 2022. In July 2021, Intel presented brand new process technology roadmap, according to which "Intel 3" process (previously named Intel 7+), the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, was at that temporal juncture scheduled to enter product manufacturing phase in H2 2023. In June 2022, Samsung started "initial" production of a low-power, high-performance chip using 3 nm process technology with GAA architecture. According to industry sources, Qualcomm had at that juncture reserved some "3 nm" production capacity from Samsung. On 25 July 2022, Samsung celebrated the first shipment of "3 nm Gate-All-Around" chips to a Chinese cryptocurrency mining firm PanSemi. It was revealed that the newly introduced "3 nm" MBCFET process technology offers 16% higher transistor density, 23% higher performance or 45% lower power draw compared to an unspecified 5 nm process technology. Goals for the second-generation "3 nm" process technology include up to 35% higher transistor density, The company planned at that juncture to have been going to start volume manufacturing using refined "3 nm" process technology called N3E in the second half of 2023. In December 2022, at IEDM 2022 conference, TSMC disclosed a few details about their "3 nm" process technologies: contacted gate pitch of N3 is 45 nm, minimum metal pitch of N3E is 23 nm, and SRAM cell area is 0.0199 μm2 for N3 and 0.021 μm2 for N3E (same as in N5). For N3E process, depending on the number of fins in cells used for design, area scaling compared to N5 2–2 fin cells ranges from 0.64x to 0.85x, performance gains range from 11% to 32% and energy savings range from 12% to 30% (the numbers refer to Cortex-A72 core). TSMC's FinFlex technology allowed at that juncture to intermix cells with different number of fins in a single chip. Reporting from IEDM 2022, semiconductor industry expert Dick James stated that TSMC's "3 nm" processes offered only incremental improvements, because limits had at that juncture been reached for fin height, gate length, and number of fins per transistor (single fin). After implementation of features such as single diffusion break, contact over active gate and FinFlex, there would have imminently posterior to that juncture been no more room left for improvement of FinFET-based process technologies. In April 2023, at its Technology Symposium, TSMC revealed some details about their N3P and N3X processes the company had introduced earlier: N3P was at that juncture projected to offer 5% higher speed or 5–10% lower power and 1.04× higher "chip density" compared to N3E, while N3X was at that juncture reported or projected to offer 5% speed gain at the cost of ~3.5× higher leakage and the same density compared to N3P. N3P was at that juncture scheduled to enter volume production in the second half of 2024, and N3X was at that juncture expected or projected to follow in 2025. In July 2023, semiconductor industry research firm TechInsights said it had at that juncture found that Samsung's 3 nm GAA (gate-all-around) process had at that juncture been incorporated into the crypto miner ASIC (Whatsminer M56S++) from a Chinese manufacturer, MicroBT. On 7 September 2023, MediaTek and TSMC announced that MediaTek had at that juncture developed their first 3 nm chip, volume production was at that juncture expected to commence in 2024. On 22 May 2025, Xiaomi announced its first 3 nm chip XRING O1, volume production under TSMC N3E process, which at that juncture had been equipped on its Xiaomi 15S Pro phone and Xiaomi Pad 7 Ultra. ==3 nm process nodes==