MOS Technology 6502

Genesis at Motorola Motorola started the 6800 microprocessor project in 1971 with Tom Bennett as the main architect. Bennett hired Chuck Peddle in 1973 to do architectural support work on the 6800 family products already in progress. Bennett already was at work on what became the 6800. "He hired me," Peddle says of Bennett, "to do the architectural support work for the product he'd already started." … Peddle says. "Motorola tried to kill it several times. Without Bennett, the 6800 would not have happened, and a lot of the industry would not have happened, either." Peddle contributed in many areas, including the design of the 6850 ACIA (serial interface). Peddle would accompany Motorola salespeople on customer visits, and found that customers were put off by the high cost of the microprocessor chips. At the same time, these visits invariably resulted in the engineers he presented to producing lists of required instructions that were much smaller than "all these fancy instructions" that had been included in the 6800. Peddle and other team members started outlining the design of an improved feature, reduced-size microprocessor. At that time, Motorola's new semiconductor fabrication facility in Austin, Texas, was having difficulty producing MOS chips, and mid-1974 was the beginning of a year-long recession in the semiconductor industry. Also, many of the Mesa, Arizona employees were displeased with the upcoming relocation to Austin. Motorola's Semiconductor Products Division management showed no interest in Peddle's low-cost microprocessor proposal. Eventually, Peddle was given an official letter telling him to stop working on the system. Peddle responded to the order by informing Motorola that the letter represented an official declaration of "project abandonment", and as such, the intellectual property he had developed to that point was now his. The 6502 was designed by many of the same engineers that had designed the Motorola 6800 microprocessor family. In a November 1975 interview, Motorola's Chairman, Bob Galvin, ultimately agreed that Peddle's concept was a good one and that the division missed an opportunity, "We did not choose the right leaders in the Semiconductor Products division." The division was reorganized and the management replaced. The new group vice president John Welty said, "The semiconductor sales organization lost its sensitivity to customer needs and couldn't make speedy decisions." MOS Technology Peddle began looking outside Motorola for a source of funding for this new project. He initially approached Mostek CEO L. J. Sevin, but was declined. Sevin later admitted this was because he was afraid Motorola would sue them. While Peddle was visiting Ford Motor Company on one of his sales trips, Bob Johnson, later head of Ford's engine automation division, mentioned that their former colleague John Paivinen had moved to General Instrument and taught himself semiconductor design. Paivinen then formed MOS Technology in Valley Forge, Pennsylvania in 1969 with two other executives from General Instrument, Mort Jaffe and Don McLaughlin. Allen-Bradley, a supplier of electronic components and industrial controls, acquired a majority interest in 1970. The company designed and fabricated custom ICs for customers and had developed a line of calculator chips. After the Mostek efforts fell through, Peddle approached Paivinen, who "immediately got it". On 19 August 1974, Chuck Peddle, Bill Mensch, Rod Orgill, Harry Bawcom, Ray Hirt, Terry Holdt, and Wil Mathys left Motorola to join MOS. Mike Janes joined later. Of the seventeen chip designers and layout people on the 6800 team, eight left. The goal of the team was to design and produce a low-cost microprocessor for embedded applications and to target as wide as possible a customer base. This would be possible only if the microprocessor was low cost, and the team set the price goal for volume purchases at . Mensch later stated the goal was not the processor price itself, but to create a set of chips that could sell at to compete with the recently introduced Intel 4040 that sold for in a similar complete chipset. Chips are produced by printing multiple copies of the chip design on the surface of a wafer, a thin disk of highly pure silicon. Smaller chips can be printed in greater numbers on the same wafer, decreasing their relative price. Additionally, wafers always include some number of tiny physical defects that are scattered across the surface. Any chip printed in that location will fail and has to be discarded. Smaller chips mean any single copy is less likely to be printed on a defect. For both of these reasons, the cost of the final product is strongly dependent on the size of the chip design. The original 6800 chips were intended to be , but layout was completed at , or an area of . For the new design, the cost goal demanded a size goal of , or an area of , roughly half that of the 6800. Several new techniques would be needed to hit this goal. Moving to NMOS Two significant advances arrived in the market just as the 6502 was being designed that provided significant cost reductions. The first was the move to depletion-load NMOS. The 6800 used an early NMOS process, enhancement mode, that required three supply voltages. One of the 6800's headlining features was an onboard voltage doubler that allowed a single +5 V supply be used for +5, −5 and +12 V internally, as opposed to other chips of the era like the Intel 8080 that required three separate supply pins. While this feature reduced the complexity of the power supply and pin layout, it still required separate power line to the various gates on the chip, driving up complexity and size. By moving to the new depletion-load design, a single +5 V supply was all that was needed, eliminating all of this complexity. A further advantage was that depletion-load designs used less power while switching, thus running cooler and allowing higher operating speeds. Another practical offshoot is that the clock signal for earlier CPUs had to be strong enough to survive all the dissipation as it traveled through the circuits, which almost always required a separate external chip that could supply a powerful signal. With the reduced power requirements of depletion-load design, the clock could be moved onto the chip, simplifying the overall computer design. These changes greatly reduced complexity and the cost of implementing a complete system. A wider change taking place in the industry was the introduction of projection masking. Previously, chips were patterned onto the surface of the wafer by placing a mask on the surface of the wafer and then shining a bright light on it. The masks often picked up tiny bits of dirt or photoresist as they were lifted off the chip, causing flaws in those locations on any subsequent masking. With complex designs like CPUs, 5 or 6 such masking steps would be used, and the chance that at least one of these steps would introduce a flaw was very high. In most cases, 90% of such designs were flawed, resulting in a 10% yield. The price of the working examples had to cover the production cost of the 90% that were thrown away. In 1973, Perkin-Elmer introduced the Micralign system, which projected an image of the mask on the wafer instead of requiring direct contact. Masks no longer picked up dirt from the wafers and lasted on the order of 100,000 uses rather than 10. This eliminated step-to-step failures and the high flaw rates formerly seen on complex designs. Yields on CPUs immediately jumped from 10% to 60 or 70%. This meant the price of the CPU declined roughly the same amount and the microprocessor suddenly became a commodity device. Design notes Chuck Peddle, Rod Orgill, and Wil Mathys designed the initial architecture of the new processors. A September 1975 article in EDN magazine gives this summary of the design: The MOS Technology 650X family represents a conscious attempt of eight former Motorola employees who worked on the development of the 6800 system to put out a part that would replace and outperform the 6800, yet undersell it. With the benefit of hindsight gained on the 6800 project, the MOS Technology team headed by Chuck Peddle, made the following architectural changes in the Motorola CPU… The main change in terms of chip size was the elimination of the tri-state drivers from the address bus outputs. A three-state bus has states for 1, 0 and high impedance. The last state is used to allow other devices to access the bus, and is typically used for multiprocessing, or more commonly in these roles, for direct memory access (DMA). While useful, this feature is expensive in terms of on-chip circuitry. The 6502 simply removed this feature, in keeping with its design as an inexpensive controller being used for specific tasks and communicating with simple devices. Peddle suggested that anyone who required this style of access could implement it with a 74158. The next major difference was to simplify the registers. To start with, one of the two accumulators was removed. General-purpose registers like accumulators have to be accessed by many parts of the instruction decoder, and thus require significant amounts of wiring to move data to and from their storage. Two accumulators makes many coding tasks easier but costs the chip design itself significant complexity. Further savings were made by reducing the stack register from 16 to 8 bits, meaning that the stack could only be 256 bytes long, which was enough for its intended role as a microcontroller. The 16-bit IX index register was split in two, becoming X and Y. More importantly, the style of access changed. In the 6800, IX held a 16-bit address which was offset by an 8-bit number stored with the instruction and added to the address. In the 6502 (and most other contemporary designs), the 16-bit base address was stored in the instruction, and the 8-bit X or Y was added to it. Finally, the instruction set was simplified, simplifying the decoder and control logic. Of the original 72 instructions in the 6800, 56 were implemented. Among those removed were instructions that operated between the 6800's two accumulators, and several branch instructions inspired by the PDP-11. The chip's high-level design had to be turned into drawings of transistors and interconnects. At MOS Technology, the layout was a very manual process done with colored pencils and vellum paper. The layout consisted of thousands of polygon shapes on six different drawings; one for each layer of the fabrication process. Given the size limits, the entire chip design had to be constantly considered. Mensch and Paivinen worked on the instruction decoder while Mensch, Peddle and Orgill worked on the ALU and registers. A further advance, developed at a party, was a way to share some of the internal wiring to allow the ALU to be reduced in size. Despite their best efforts, the final design ended up being larger than the original target. The first 6502 chips were , for an area of . The original version of the processor had no rotate right (ROR) capability, so the instruction was omitted from the original documentation. The next iteration of the design shrank the chip and added the rotate right capability, and ROR was included in revised documentation. Introducing the 6501 and 6502 MOS would introduce two microprocessors based on the same underlying design: the 6501 would plug into the same socket as the Motorola 6800, while the 6502 re-arranged the pinout to support an on-chip clock oscillator. Both would work with other support chips designed for the 6800. They would not run 6800 software because they had a different instruction set, different registers, and mostly different addressing modes. Stories also ran in EE Times (August 24, 1975), EDN (September 20, 1975), Electronic News (November 3, 1975), Byte (November 1975) and Microcomputer Digest (November 1975). Advertisements for the 6501 appeared in several publications the first week of August 1975. The 6501 would be for sale at WESCON for each. In September 1975, the advertisements included both the 6501 and the 6502 microprocessors. The 6502 would cost only (). When MOS Technology arrived at Wescon, they found that exhibitors were not permitted to sell anything on the show floor. They rented the MacArthur Suite at the St. Francis Hotel and directed customers there to purchase the processors. At the suite, the processors were stored in large jars to imply that the chips were in production and readily available. The customers did not know the bottom half of each jar contained non-functional chips. The chips were and while the documentation package was an additional . Users were encouraged to make photocopies of the documents, an inexpensive way for MOS Technology to distribute product information. The preliminary data sheets listed just 55 instructions and excluded the Rotate Right (ROR) instruction, which was not supported on these early chips. The reviews in Byte and EDN noted the lack of the ROR instruction. The next revision of the layout fixed this problem and the May 1976 datasheet listed 56 instructions. Peddle wanted every interested engineer and hobbyist to have access to the chips and documentation, whereas other semiconductor companies only wanted to deal with "serious" customers. For example, Signetics was introducing the 2650 microprocessor and its advertisements asked readers to write for information on their company letterhead. Motorola lawsuit version. The 6501/6502 introduction in print and at Wescon was a success. The press coverage got Motorola's attention, precipitating pricing adjustments and lawsuits. In October 1975, Motorola reduced the price of a single 6800 microprocessor from to . The system design kit was reduced to and it now came with a printed circuit board. On November 3, 1975, Motorola sought an injunction in Federal Court to stop MOS Technology from making and selling microprocessor products. They also filed a lawsuit claiming patent infringement and misappropriation of trade secrets. Motorola claimed that seven former employees joined MOS Technology to create that company's microprocessor products. Motorola was a billion-dollar company with a plausible case and expensive lawyers. On October 30, 1974, Motorola had filed numerous patent applications on the microprocessor family and was granted twenty-five patents. The first was in June 1976 and the second was to Bill Mensch on July 6, 1976, for the 6820 PIA chip layout. These patents covered the 6800 bus and how the peripheral chips interfaced with the microprocessor. Motorola began making transistors in 1950 and had a portfolio of semiconductor patents. Allen-Bradley decided not to fight this case and sold their interest in MOS Technology back to the founders. Four of the former Motorola engineers were named in the suit: Chuck Peddle, Will Mathys, Bill Mensch and Rod Orgill. All were named inventors in the 6800 patent applications. During the discovery process, Motorola found that one engineer, Mike Janes, had ignored Peddle's instructions and brought his 6800 design documents to MOS Technology. In March 1976, the now independent MOS Technology was running out of money and had to settle the case. They agreed to drop the 6501 processor, pay Motorola and return the documents that Motorola contended were confidential. Both companies agreed to cross-license microprocessor patents. That May, Motorola dropped the price of a single 6800 microprocessor to . By November, Commodore had acquired MOS Technology. Computers and games With legal troubles behind them, MOS was still left with the problem of getting developers to try their processor, prompting Chuck Peddle to design the MDT650 development system. Another group inside the company designed the KIM-1, which was sold semi-complete and could be turned into a usable system with the addition of a 3rd party computer terminal and compact cassette drive. While it sold well to its intended market, the company found the KIM-1 also sold well to hobbyists and tinkerers. The related Rockwell AIM-65 control, training, and development system also did well. The software in the AIM 65 was based on that in the MDT. Another roughly similar product was the Synertek SYM-1. One of the first external uses for the design was the Apple I microcomputer, introduced in 1976. The 6502 was next used in the Commodore PET and Apple II, both released in 1977. It was later used in the Atari 8-bit computers, Acorn Atom, BBC Micro, Commodore 64 home computer. Another important use of the 6500 family was in video games. The first to make use of the processor design was the 1977 Atari VCS, later renamed the Atari 2600. The VCS used a 6502 variant named the 6507, which had fewer pins, so it could address only 8 KB of memory. Millions of the Atari consoles would be sold, each with a MOS processor. Another significant use was by the Nintendo Entertainment System (NES) and Famicom. The 6502 used in the NES was a second source version by Ricoh, a partial system on a chip, that lacked the binary-coded decimal mode but added 22 memory-mapped registers and on-die hardware for sound generation, joypad reading, and sprite list DMA. Called 2A03 in NTSC consoles and 2A07 in PAL consoles, this processor was produced exclusively for Nintendo. 6502 or variants were used in all of Commodore's floppy disk drives for all of their 8-bit computers, from the PET line through the Commodore 128D, including the Commodore 64. 8-inch PET drives had two 6502 processors. Atari used the same 6507 used in the Atari 2600 for its 810 and 1050 disk drives used for all of their 8-bit computer line, from the 400/800 through the XEGS. In the 1980s, a popular electronics magazine Elektor used the processor in its microprocessor development board Junior Computer. The CMOS successor to the 6502, the WDC 65C02, also saw use in home computers and video game consoles. Apple used it in the Apple II line, starting with the Apple IIc and later variants of the Apple IIe, and also offered a kit to upgrade older IIe systems with the new processor. The Hudson Soft HuC6280 chip used in the TurboGrafx-16 was based on a 65C02 core. The Atari Lynx used a custom chip named "Mikey" designed by Epyx which included a VLSI VL65NC02 licensed cell. The G65SC12 by GTE Microcircuits (renamed California Micro Devices) variant was used in the BBC Master. Some models of the BBC Master also included an additional G65SC102 co-processor. File:Acorn atom zx1.jpg|Acorn Atom File:Acorn Electron 4x3.jpg|Acorn Electron File:CopsonApple1 2k cropped.jpg|Apple I File:Apple II tranparent 800.png|Apple II File:Apple IIe.jpg|Apple IIe File:Atari-2600-Console.jpg|Atari 2600 File:Atari-5200-4-Port-wController-L.jpg|Atari 5200 File:Atari-7800-Console-Set.jpg|Atari 7800 File:Atari-800-Computer-FL.jpg|Atari 800 File:Atari-Lynx-I-Handheld.jpg|Atari Lynx File:Acorn BBC Master Series.jpg|BBC Master File:STM Systems Baby! 1 computer.jpg|Baby! 1 File:BBC Micro Front Restored.jpg|BBC Micro File:Commodore 2001 Series-IMG 0448b.jpg|Commodore PET File:Commodore-VIC-20-FL.jpg|Commodore VIC-20 File:Commodore-64-Computer-FL.jpg|Commodore 64 File:Commodore-128.jpg|Commodore 128 File:Nintendo-Famicom-Console-Set-FL.jpg|Family Computer (Famicom) File:NES-Console-Set.jpg|Nintendo Entertainment System File:OSI Challenger 4P.jpg|Ohio Scientific Challenger 4P File:Orao-IMG 7278.jpg|Orao File:Oric1.jpg|Oric-1 File:Oric Atmos 01a.jpg|Oric Atmos File:TurboGrafx16-Console-Set.jpg|TurboGrafx-16 ==Programmers model==

) The 6502 is a little-endian 8-bit processor with a 16-bit address bus. The original versions were fabricated using an process technology with a die size of , for a total area of . The internal logic runs at the same speed as the external clock rate. It featured a simple two-stage pipeline; on each cycle, the processor fetches one byte from memory and processes another. This means that any single instruction can take as few as two cycles to complete, depending on the number of operands that instruction uses. For comparison, the Zilog Z80 required two cycles to fetch memory, and the minimum instruction time was four cycles. Thus, despite the lower clock speeds compared to competing designs, typically in the neighborhood of 1 to , the 6502's performance was competitive with CPUs using significantly faster clocks. This is partly due to a simple state machine implemented by combinational (clockless) logic to a greater extent than in many other designs; the two-phase clock (supplying two synchronizations per cycle) could thereby control the machine cycle directly. This design also led to one useful design note of the 6502, and the 6800 before it. Because the chip only accessed memory during a certain part of the clock cycle, other chips in a system could access memory during those times when the 6502 was off the bus. This was sometimes known as hidden access. This technique was widely used by computer systems; they would use memory capable of access at 2 MHz, and then run the CPU at 1 MHz. This guaranteed that the CPU and video hardware could interleave their accesses, with a total performance matching that of the memory device. Because this access was every other cycle, there was no need to signal the CPU to avoid using the bus, making this sort of access easy to implement without any bus logic. When faster memories became available in the 1980s, newer machines could use this same technique while running at higher clock rates; the BBC Micro used newer RAM that allowed its CPU to run at 2 MHz while still using the same bus sharing techniques. Like most simple CPUs of the era, the dynamic NMOS 6502 chip is not sequenced by microcode but decoded directly using a dedicated PLA. The decoder occupied about 15% of the chip area. This compares to later microcode-based designs like the Motorola 68000, where the microcode ROM and decoder engine represented about a third of the gates in the system. Registers Like its precursor, the 6800, the 6502 has very few registers. They include • A = 8-bit accumulator • P = 7-bit processor status • n = Negative • v = Overflow • b = Break (only in stack values, not in hardware) • d = Decimal • i = Interrupt disable • z = Zero • c = Carry • PC = 16-bit program counter • S = 8-bit stack pointer • X = 8-bit index • Y = 8-bit index This compares to a contemporaneous competitor, the Intel 8080, which likewise has one 8-bit accumulator and a 16-bit program counter, but has six more general-purpose 8-bit registers (which can be combined into three 16-bit pointers) and a larger 16-bit stack pointer. In order to make up somewhat for the lack of registers, the 6502 includes a zero page addressing mode that uses one address byte in the instruction instead of the two needed to address the full of memory. This provides fast access to the first of RAM by using shorter instructions. For instance, an instruction to add a value from memory to the value in the accumulator would normally be three bytes, one for the instruction and two for the 16-bit address. Using the zero page reduces this to an 8-bit address, reducing the total instruction length to two bytes, and thus improving instruction performance. The stack address space is hardwired to memory page $01, i.e. the address range $0100–$01FF (256–511). Software access to the stack is done via four implied addressing mode instructions, whose functions are to push or pop (pull) the accumulator or the processor status register. The same stack is also used for subroutine calls via the JSR (jump to subroutine) and RTS (return from subroutine) instructions and for interrupt handling. Addressing The chip uses the index and stack registers effectively with several addressing modes, including a fast zero page mode, similar to that found on the PDP-8, that accesses memory locations from addresses 0 to 255 with a single 8-bit address (saving the cycle normally required to fetch the high-order byte of the address)code for the 6502 uses the zero page much as code for other processors would use registers. On some 6502-based microcomputers with an operating system, the operating system uses most of the zero page, leaving only a handful of locations for the user. Addressing modes also include implied (1-byte instructions); absolute (3 bytes); indexed absolute (3 bytes); indexed zero-page (2 bytes); relative (2 bytes); accumulator (1); indirect,x and indirect,y (2); and immediate (2). Branch instructions use a signed 8-bit offset relative to the instruction after the branch; the numerical range −128..127 therefore translates to 128 bytes backward and 127 bytes forward from the instruction following the branch (which is 126 bytes backward and 129 bytes forward from the start of the branch instruction). Accumulator mode operates on the accumulator register and does not need any operand data. Immediate mode uses an 8-bit literal operand. The indirect modes are useful for array processing and pointer-based data structures. With the 5 or 6 cycle indirect,y mode, the 8-bit Y register is added to a 16-bit base address read from zero page, which is located by a single byte following the opcode. The Y register is therefore an index register in the sense that it is used to hold an actual index. Incrementing the index register to walk the array byte-wise takes only two additional cycles. With the less frequently used indirect,x mode, the effective address for the operation is found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acts as a set of up to 128 additional (low-performance) address registers. The 6502 is capable of performing addition and subtraction in binary or binary-coded decimal. Placing the CPU into BCD mode with the SED (set D flag) instruction results in decimal arithmetic, in which $99 + $01 would result in $00 and the carry (C) flag being set. In binary mode (CLD, clear D flag), the same operation would result in $9A and the carry flag being cleared. Other than Atari BASIC, BCD mode was seldom used in home-computer applications. See the Hello world! article for a simple but characteristic example of 6502 assembly language. Instructions and opcodes 6502 instruction operation codes (opcodes) are 8 bits long and have the general form AAABBBCC, where AAA and CC define the opcode, and BBB defines the addressing mode. For example, the ORA instruction performs a bitwise OR on the bits in the accumulator with another value. The instruction opcode is of the form 000bbb01, where bbb may be 010 for an immediate mode value (constant), 001 for zero-page fixed address, 011 for an absolute address, and so on. The operand is stored in the 6502's customary little-endian format. Each CPU machine instruction takes up a certain number of clock cycles, usually equal to the number of memory accesses. For example, the absolute indexing mode of the ORA instruction takes 4 clock cycles; 3 cycles to read the instruction and 1 cycle to read the value of the absolute address. If no memory is accessed, the number of clock cycles is two. The minimum clock cycles for any instruction is two. When using indexed addressing, if the result crosses a page boundary an extra clock cycle is added. Also, when a zero page address is used in indexing mode (e.g. zp,X) an extra clock cycle is added. The 65C816, the 16-bit CMOS descendant of the 6502, also supports 24-bit addressing, which results in instructions being assembled with three-byte operands, also arranged in little-endian format. The remaining 105 opcodes are undefined. In the original design, instructions where the low-order 4 bits (nibble) were 3, 7, B or F were not used, providing room for future expansion. Likewise, the $x2 column had only a single entry, LDX #constant. The remaining 25 empty slots were distributed. Some of the empty slots were used in the 65C02 to provide both new instructions and variations on existing ones with new addressing modes. The $xF instructions were initially left free to allow 3rd-party vendors to add their own instructions, but later versions of the 65C02 standardized a set of bit manipulation instructions developed by Rockwell Semiconductor. Assembly language A 6502 assembly language statement consists of a three-character instruction mnemonic, followed by any operands. Instructions that do not take a separate operand but target a single register based on the addressing mode combine the target register in the instruction mnemonic, so the assembler uses INX as opposed to INC X to increment the X register. Instruction table Example code The following 6502 assembly language source code is for a subroutine named TOLOWER, which copies a null-terminated character string from one location to another, converting upper-case letter characters to lower-case letters. The string being copied is the "source", and the string into which the converted source is stored is the "destination". ==IC hardware design==

The processor's non-maskable interrupt (NMI) input is edge sensitive, which means that the interrupt is triggered by the falling edge of the signal rather than its level. Consequently a wired-OR interrupt circuit cannot be readily supported. However, this also prevents nested NMI interrupts from occurring until the interrupt source hardware makes the NMI input inactive again, often under control of the NMI interrupt handler. The simultaneous assertion of the NMI and IRQ (maskable) hardware interrupt lines causes IRQ to be ignored. However, if the IRQ line remains asserted after the servicing of the NMI, the processor will almost immediately respond to IRQ, as IRQ is level sensitive. Thus a sort of built-in interrupt priority was established in the 6502 design. (The first opcode of the NMI handler is executed before the IRQ is detected again.) The B flag is set by the 6502's periodically sampling its NMI edge detector's output and its IRQ input. The IRQ signal being driven low is only recognized though if IRQs are not masked by the I flag. If in this way a NMI request or (maskable) IRQ is detected the B flag is set to zero and causes the processor to execute the BRK instruction next instead of executing the next instruction based on the program counter. The BRK instruction then pushes the processor status onto the stack, with the B flag bit set to zero. At the end of its execution the BRK instruction resets the B flag's value to one. This is the only way the B flag can be modified. If an instruction other than the BRK instruction pushes the B flag onto the stack as part of the processor status the B flag always has the value one. A high-to-low transition on the SO input pin will set the processor's overflow status bit. This can be used for fast response to external hardware. For example, a high-speed polling device driver can poll the hardware once in only three cycles using a Branch-on-oVerflow-Clear (BVC) instruction that branches to itself until overflow is set by an SO falling transition. The Commodore 1541 and other Commodore floppy disk drives use this technique to detect when the serializer is ready to transfer another byte of disk data. The system hardware and software design must ensure that an SO will not occur during arithmetic processing and disrupt calculations. ==Variations and derivatives ==

The 6502 was the most prolific variant of the 65xx series family from MOS Technology. The 6501 and 6502 have 40-pin DIP packages; the 6503, 6504, 6505, and 6507 are 28-pin DIP versions, for reduced chip and circuit board cost. In all of the 28-pin versions, the pin count is reduced by leaving off some of the high-order address pins and various combinations of function pins, making those functions unavailable. Typically, the 12 pins omitted to reduce the pin count from 40 to 28 are the three not connected (NC) pins, one of the two Vss pins, one of the clock pins, the SYNC pin, the set overflow (SO) pin, either the maskable interrupt or the non-maskable interrupt (NMI), and the four most-significant address lines (A12–A15). The omission of four address pins reduces the external addressability to 4 KB (from the 64 KB of the 6502), though the internal PC register and all effective address calculations remain 16-bit. The 6507 omits both interrupt pins in order to include address line A12, providing 8 KB of external addressability but no interrupt capability. The 6507 was used in the popular Atari 2600 video game console, the design of which divides the 8 KB memory space in half, allocating the lower half to the console's internal RAM and peripherals, and the upper half to the Game Cartridge, so Atari 2600 cartridges have a 4 KB address limit (and the same capacity limit unless the cartridge contains bank switching circuitry). One popular 6502-based computer, the Commodore 64, used a modified 6502 CPU, the 6510. Unlike the 6503–6505 and 6507, the 6510 is a 40-pin chip that adds internal hardware: a 6-bit parallel I/O port mapped to addresses 0000 and 0001. The 6508 is another chip that, like the 6510, adds internal hardware: 256 bytes of SRAM and an 8-bit I/O port similar to those featured by the 6510. Though these chips do not have reduced pin counts compared to the 6502, they need new pins for the added parallel I/O port. In this case, no address lines are among the removed pins. 16-bit derivatives The Western Design Center designed and, , still produces the WDC 65C816S processor, a 16-bit, static-core successor to the 65C02. The W65C816S is a newer variant of the 65C816, which is the core of the Apple IIGS computer and is the basis of the Ricoh 5A22 processor that powers the Super Nintendo Entertainment System. The W65C816S incorporates minor improvements over the 65C816 that make the newer chip not an exact hardware-compatible replacement for the earlier one. Among these improvements was conversion to a static core, which makes it possible to stop the clock in either phase without the registers losing data. Available through electronics distributors, as of March 2020, the W65C816S is officially rated for 14 MHz operation. The Western Design Center also designed and produced the 65C802, which was a 65C816 core with a 64-kilobyte address space in a 65(C)02 pin-compatible package. The 65C802 could be retrofitted to a 6502 board and would function as a 65C02 on power-up, operating in "emulation mode." As with the 65C816, a two-instruction sequence would switch the 65C802 to "native mode" operation, exposing its 16-bit accumulator and index registers, and other 65C816 features. The 65C802 was not widely used and production ended. ==Bugs and quirks==

The 6502 had several bugs and quirks, which had to be accounted for when programming it: • The earliest revisions of the 6502, such as those shipped with some KIM-1 computers, did not have a ROR (rotate right memory or accumulator) instruction. In these chips, the operation of the opcode that was later assigned to ROR is effectively an ASL (arithmetic shift left) instruction that does not affect the carry bit in the status register. Initially, MOS intentionally excluded ROR from the instruction set, deeming it not of enough value to justify its costs. In reaction to many customer inquiries, MOS promised in the second edition of the MCS6500 Programming Manual (document no. 6500-50A) that ROR would appear in 6502 chips starting in 1976. All of the undefined opcodes have been replaced with NOP instructions in the 65C02, an enhanced CMOS version of the 6502, although with varying byte sizes and execution times. (Some of them actually perform memory read operations but then ignore the data.) In the 65C802/65C816, all 256 opcodes perform defined operations. • The 6502's memory indirect jump instruction, JMP (<address>), has a nonintuitive limitation which many users consider a defect. If <address> is hex xxFF (i.e., any word ending in FF), the processor will not jump to the address stored in xxFF and xxFF+1 as expected, but rather the one defined by xxFF and xx00 (for example, would jump to the address stored in and , instead of the one stored in and ). This can be avoided simply by not placing any indirect jump target address across a page boundary, and the MOS Technology MCS6500 Programming Manual gives reason to believe that this was the intention of the designers of the 6502, in order to save space on the chip that would have been used to implement the more complex behavior of conditionally adding 1 clock cycle to propagate the carry when necessary. This ostensible defect continued through the entire NMOS line but was corrected in the CMOS derivatives. • The NMOS 6502 indexed addressing across page boundaries will do an extra read of an invalid address in the page of the base address (to which the index is added). This characteristic may cause random issues by accessing hardware that acts on a read, such as clearing timer or IRQ flags, sending an I/O handshake, etc. The extra read can be predicted and managed to avoid such problems, but only with special care in both hardware and software design. This flaw continued through the entire NMOS line but was corrected in the CMOS derivatives, in which the processor does an extra read of the last instruction byte. • The 6502 read–modify–write instructions perform one read and two write cycles. First, the unmodified data that was read is written back, and then the modified data is written. This characteristic may cause issues by twice accessing hardware that acts on a write. This anomaly continued through the full NMOS line but was fixed in the CMOS derivatives, in which the processor does two reads and one write cycle. Defensive programming practice will generally avoid this problem by not executing read/modify/write instructions on hardware registers. • The N (result negative), V (sign bit overflow) and Z (result zero) status flags are generally meaningless when performing arithmetic operations while the processor is in BCD mode, as these flags are undefined in decimal mode and have been empirically shown to reflect the binary, not BCD, result. This limitation was removed in the CMOS derivatives, at the cost of one added clock cycle for an ADC or SBC instruction in decimal mode (except on the 65C816). Therefore, this feature may be used to distinguish a CMOS processor from an NMOS version (by relying on the undocumented behavior of the NMOS version). • If the 6502 happens to be in BCD mode when a hardware interrupt occurs, it will not revert to binary mode. This characteristic could result in obscure bugs in the interrupt service routine (ISR) if it fails to clear BCD mode before performing any arithmetic operations. The 6502 programming manual thus requires each ISR to reset or set the D flag if it uses the ADC or SBC instruction, but occasionally a human programmer may mistakenly omit to do this, causing a bug. For example, the Commodore 64's KERNAL did not correctly handle this processor characteristic, requiring that IRQs be disabled or re-vectored during BCD math operations. This issue was addressed in the CMOS derivatives also, by making reset and all interrupts automatically reset the D flag. (The change has the one disadvantage that it makes a [rare] program that operates continuously in decimal mode slightly longer and slower, as now every ISR must set the D flag before executing ADC or SBC.) • The 6502 instruction set includes BRK (opcode ), which is technically a software interrupt (similar in spirit to the SWI mnemonic of the Motorola 6800 and ARM processors). BRK is most often used to interrupt program execution and start a machine language monitor for testing and debugging during software development. BRK could also be used to route program execution using a simple jump table (analogous to the manner in which the Intel 8086 and derivatives handle software interrupts by number). However, if a maskable hardware interrupt occurs when the processor is fetching a BRK instruction, the NMOS version of the processor will fail to execute BRK and instead proceed as if only the hardware interrupt had occurred. This fault—an unequivocal hardware bug—was corrected in the CMOS implementation of the processor, which first calls the ISR for the hardware interrupt and then executes the BRK instruction. • When executing JSR (jump to subroutine) and RTS (return from subroutine) instructions, the return address pushed to the stack by JSR is that of the last byte of the JSR operand (that is, the most significant byte of the subroutine address), rather than the address of the following instruction. This is because the actual copy (from program counter to stack and then conversely) takes place before the automatic increment of the program counter that occurs at the end of every instruction. This characteristic would go unnoticed unless the code examined the return address in order to retrieve parameters in the code stream. It remains a characteristic of 6502 derivatives to this day. The original MCS6500 Programming Manual points it out and explains the reason: it saves one clock cycle in the JSR by not incrementing the PC before pushing it, while in the RET instruction, the deferred increment of the pulled PC is overlapped with other steps and adds no clock cycle. As designed, a JSR and RET take 12 clock cycles total; if the JSR pushed the incremented PC, the call and return would take 13 clock cycles. To do an indirect branch, an address-1 is loaded from a table, pushed onto the stack, and then RTS. • The SBC instruction (Subtract Memory from Accumulator with Borrow) uses inverted carry as borrow. A zero carry flag is used to signal borrow from previous subtract. If a borrow is not desired, the carry bit must be set before the SBC instruction. This way the ALU subtract logic can reuse the add logic with just inverted second input which saves a lot of gates. • The read access of the CPU can be delayed by setting the RDY pin to low temporarily. However, during write access, which can take up to three consecutive clock cycles for a BRK instruction, the CPU will stop only in the next read cycle. This quirk was corrected in the CMOS derivatives and also in the 6510 and its variants. ==See also==