Athlon 64

The Athlon 64 was originally codenamed ClawHammer by AMD, Like the Opteron, on which it was based, the Athlon FX-51 required buffered random-access memory (RAM), increasing the final cost of an upgrade. The week of the Athlon 64's launch, Intel released the Pentium 4 Extreme Edition, a CPU designed to compete with the Athlon 64 FX. The Extreme Edition was widely considered a marketing ploy to draw publicity away from AMD, and was quickly nicknamed among some circles the "Emergency Edition". Despite a very strong demand for the chip, AMD experienced early manufacturing difficulties that made it difficult to deliver Athlon 64s in quantity. In the early months of the Athlon 64 lifespan, AMD could only produce 100,000 chips per month. However, it was very competitive in terms of performance to the Pentium 4, with PC World calling it the "fastest yet". The Athlon FX-51 was also outperforming the Pentium 4 3.2C in Quake III Arena and Unreal Tournament 2003 benchmark, according to Maximum PC. "Newcastle" was released soon after ClawHammer, with half the Level 2 cache. Single-core Athlon 64 processors available to the general consumer market. All the 64-bit processors sold by AMD so far have their genesis in the K8 or Hammer project. On June 1, 2004, AMD released new versions of both the ClawHammer and Newcastle core revisions for the newly introduced Socket 939, an altered Socket 940 without the need for buffered memory. Socket 939 offered two main improvements over Socket 754: the memory controller was altered with dual-channel architecture, doubling peak memory bandwidth, and the HyperTransport bus was increased in speed from 800 MHz to 1000 MHz. Socket 939 also was introduced in the FX series in the form of the FX-55. At the same time, AMD also began to ship the "Winchester" core, based on a 90 nanometer process. Core revisions "Venice" and "San Diego" succeeded all prior revisions on April 15, 2005. Venice, the lower-end part, was produced for both Sockets 754 and 939, and included 512 kB of L2 cache. San Diego, the higher-end chip, was produced only for Socket 939 and doubled Venice's L2 cache to 1 MB. Both were produced on the 90 nm fabrication process. Both also included support for the SSE3 instruction set, a new feature that had been included in the rival Pentium 4 since the release of the Prescott core in February 2004. In addition, AMD overhauled the memory controller for this revision, resulting in performance improvements as well as support for newer DDR SDRAM. Dual-core Athlon 64 On April 21, 2005, less than a week after the release of Venice and San Diego, AMD announced its next addition to the Athlon 64 line, the Athlon 64 X2. Released on May 31, 2005, it also initially had two different core revisions available to the public, Manchester and Toledo, the only appreciable difference between them being the amount of L2 cache. Both were released only for Socket 939. The Athlon 64 X2 was received very well by reviewers and the general public, with a general consensus emerging that AMD's implementation of multi-core was superior to that of the competing Pentium D. Some felt initially that the X2 would cause market confusion with regard to price points since the new processor was targeted at the same "enthusiast," US$350 and above market already occupied by AMD's existing socket 939 Athlon 64s. AMD's official breakdown of the chips placed the Athlon X2 aimed at a segment they called the "prosumer", along with digital media fans. Following the launch of the Athlon 64 X2, AMD surpassed Intel in US retail sales for a period of time, although Intel retained overall market leadership because of its exclusive relationships with direct sellers such as Dell. DDR2 The Athlon 64 had been maligned by some critics for some time because of its lack of support for DDR2 SDRAM, an at the time emerging technology that had been adopted much earlier by Intel. AMD's official position was that the CAS latency on DDR2 had not progressed to a point where it would be advantageous for the consumer to adopt it. AMD finally remedied this gap with the "Orleans" core revision, the first Athlon 64 to fit Socket AM2, released on May 23, 2006. "Windsor", an Athlon 64 X2 revision for Socket AM2, was released concurrently. Both Orleans and Windsor have either 512 kB or 1 MB of L2 cache per core. The Athlon 64 FX-62 was also released concurrently on the Socket AM2 platform. Socket AM2 also uses less power than prior platforms, and supports AMD-V. The memory controller used in all DDR2 SDRAM capable processors (Socket AM2), has extended column address range of 11 columns instead of conventional 10 columns, and the support of 16 kB page size, with at most 2048 individual entries supported. An OCZ unbuffered DDR2 kit, optimized for 64-bit operating systems, was released to exploit the functionality provided by the memory controller in socket AM2 processors, allowing the memory controller to stay longer on the same page, thus benefitting graphics intensive applications. Moving to the subnotebook space The Athlon architecture was further extended with the release of Athlon Neo processors on January 9, 2009. Based on the same architecture as the other Athlon 64 variants, the new processor features a small package footprint targeting Ultra-portable notebook market. ==Features==

There are four variants: Athlon 64, Athlon 64 FX, Mobile Athlon 64 (later renamed "Turion 64") and the dual-core Athlon 64 X2. Common among the Athlon 64 line are a variety of instruction sets including MMX, 3DNow!, SSE, SSE2, and SSE3. All Athlon 64s also support the NX bit, a security feature named "Enhanced Virus Protection" by AMD. And as implementations of the AMD64 architecture, all Athlon 64 variants are able to run 16 bit, 32 bit x86, and AMD64 code, through two different modes the processor can run in: "Legacy mode" and "long mode". Legacy mode runs 16-bit and 32-bit programs natively, and long mode runs 64-bit programs natively, but also allows for 32-bit programs running inside a 64-bit operating system. All Athlon 64 processors feature 128 Kilobytes of level 1 cache, and at least 512 kB of level 2 cache. The result is a significant reduction in latency (response time) for access requests to main memory. The lower latency was often cited as one of the advantages of the Athlon 64's architecture over those of its competitors at the time. Memory and HT Northbridge buses As the memory controller is integrated onto the CPU die, there is no FSB for the system memory to base its speed upon. Instead, system memory speed is obtained by using the following formula (using the ceiling function): :\frac{\mathrm{CPU~speed}}{\left\lceil\frac{\mathrm{CPU~multiplier}}{\mathrm{DRAM~divider}}\right\rceil}=\mathrm{DRAM~speed} In simpler terms, the memory is always running at a set fraction of the CPU speed, with the divisor being a whole number. An 'FSB' figure is still used to determine the CPU speed, but the RAM speed is no longer directly related to this 'FSB' figure (known otherwise as the LDT). A second bus, the northbridge, connected the CPU to the chipset and device attachment bus (PCIe, AGP, PCI). This was implemented using a new high-performance standard, HyperTransport. AMD attempted, with some success, to make this an industry standard. It was also useful in building multi-processor systems without additional glue chips. Translation lookaside buffers Translation lookaside buffers (TLBs) have also been enlarged (40 4k/2M/4M entries in L1 cache, 512 4k entries), with reduced latencies and improved branch prediction, with four times the number of bimodal counters in the global history counter. Cool'n'Quiet Athlon 64 also features CPU speed throttling technology branded ''Cool'n'Quiet'', a feature similar to Intel's SpeedStep that can throttle the processor's clock speed back to facilitate lower power use and heat output. When the user is running undemanding applications and the load on the processor is light, the processor clock speed and voltage are reduced. This in turn reduces its peak power use (max thermal design power (TDP) set at 89 W by AMD) to as low as 32 W (stepping level C0, clock speed reduced to 800 MHz) or 22W (stepping CG, clock speed reduced to 1 GHz). The Athlon 64 also has an integrated heat spreader (IHS) which prevents the CPU die from being damaged accidentally when mounting and unmounting heat sinks. With prior AMD CPUs, a CPU shim could be used by people worried about damaging the die. NX bit The No Execute bit (NX bit) supported by Windows XP Service Pack 2 and future versions of Windows, Linux 2.6.8 and higher and FreeBSD 5.3 and higher is also included, for improved protection from malicious buffer overflow security threats. Hardware-set permission levels make it much more difficult for malicious code to take control of the system. It is intended to make 64-bit computing a more secure environment. Semiconductor Technology The Athlon 64 CPUs have been produced with 130 and 90 nm silicon on insulator (SOI) process technologies. All of the latest chips (Winchester, Venice, and San Diego models) are on 90 nm. The Venice and San Diego models also incorporate dual stress liner technology (an amalgam of strained silicon and 'squeezed silicon', the latter of which is not actually a technology) co-developed with IBM. ==Processor cores==

Athlon 64 FX The Athlon 64 FX is positioned as a hardware enthusiast product, marketed by AMD especially toward gamers. Unlike the standard Athlon 64, all of the Athlon 64 FX processors have their multipliers completely unlocked. Starting with the FX-60, the FX line became dual-core. The FX always has the highest clock speed of all Athlons at its release. From FX-70 onwards, the line of processors will also support dual-processor setup with NUMA, named AMD Quad FX platform. Athlon 64 X2 The Athlon 64 X2 is the first dual-core desktop CPU manufactured by AMD. In 2007, AMD released two final Athlon 64 X2 versions: the AMD Athlon 64 X2 6400+ and 5000+ Black Editions. Both processors feature an unlocked multiplier, which allows for a large range of overclocked settings. The 6400+ is based on a 90 nm Windsor core (3.2 GHz, 2x1 MB L2, 125 W TDP) while the 5000+ is based on a 65 nm Brisbane core (2.6 GHz, 2 x 512 kB L2, 65 W TDP). These Black Edition processors are available at retail, but AMD does not include heatsinks in the retail package. Turion 64 (formerly Mobile Athlon 64) Formerly introduced as Mobile Athlon 64, Turion 64 is now the brand name AMD applies to its 64-bit low-power use (mobile) processors. The Turion 64 and Turion 64 X2 processors compete with Intel's mobile processors, initially the Pentium M and later the Intel Core and Intel Core 2 processors. Earlier Turion 64 processors are compatible with AMD's Socket 754. The newer "Richmond" models are designed for AMD's Socket S1. They are equipped with 512 or 1024 kB of L2 cache, a 64-bit single channel on-die memory controller, and an 800 MHz HyperTransport bus. Battery saving features, like PowerNow!, are central to the marketing and usefulness of these CPUs. Model naming methodology The model naming scheme does not make it obvious how to compare one Turion with another, or even an Athlon 64. The model name is two letters, a dash, and a two digit number (for example, ML-34). The two letters together designate a processor class, while the number represents a PR rating. The first letter is M for single core processors and T for dual core Turion 64 X2 processors. The later in the alphabet that the second letter appears, the more the model has been designed for mobility (low power use). Take for example, an MT-30 and an ML-34. Since the T in the MT-30 is later in the alphabet than the L in ML-34, the MT-30 uses less power than the ML-34. But since 34 is greater than 30, the ML-34 is faster than the MT-30. Athlon Neo With 27 mm × 27 mm in size and 2.5 mm in thickness, the Athlon Neo processors utilize a new package called "ASB1", essentially a BGA package, for smaller footprint to allow smaller designs for notebooks and lowering the cost. The clock of the processors is significantly lower than desktop and other mobile counterparts to reach a low TDP, at 15W maximum for a single core x86-64 CPU at 1.6 GHz. The Athlon Neo processors are equipped with 512 kB of L2 cache and HyperTransport 1.0 running at 800 MHz frequency. ==Sockets==

• Socket 754: The Athlon 64 value/budget line, 64-bit memory interface (Single-Channel) • Socket 939: Athlon 64 performance line, Athlon 64 X2s, and newer Athlon 64 FXs, Opteron, 128-bit memory interface (Dual-channel) • Socket 940: Opteron and old Athlon 64 FX, 128-bit memory interface - requires registered DDR memory • Socket AM2: Athlon 64/Athlon 64 FX/Athlon 64 X2/Sempron, 940 Pins (Not compatible with Socket 940); the first AMD socket to use DDR2 SDRAM. • Socket F: Opteron, 1207 Pins • Socket F (1207 FX): Athlon 64 FX on AMD Quad FX platform, also compatible for dual-processor Opteron 2200 series At the introduction of Athlon 64 in September 2003, only Socket 754 and Socket 940 (Opteron) were ready and available. The onboard memory controller was not capable of running unbuffered (non-registered) memory in dual-channel mode at the time of release; as a stopgap measure, they introduced the Athlon 64 on Socket 754, and brought out a non-multiprocessor version of the Opteron called the Athlon 64 FX, as a multiplier unlocked enthusiast part for Socket 940, comparable to Intel's Pentium 4 Extreme Edition for the high end market. In June 2004, AMD released Socket 939 as the mainstream Athlon 64 with dual-channel memory interface, leaving Socket 940 solely for the server market (Opterons), and relegating Socket 754 as a value/budget line, for Semprons and slower versions of the Athlon 64. Eventually Socket 754 replaced Socket A for Semprons. In May 2006, AMD released Socket AM2, which provided support for the DDR2 memory interface. Also, this marked the release of AMD-V. In August 2006, AMD released Socket F for Opteron server CPU which uses the LGA chip form factor. In November 2006, AMD released a specialized version of Socket F, called 1207 FX, for dual-socket, dual-core Athlon FX processors on the Quad FX platform. While Socket F Opterons already allowed for four processor cores, Quad FX allowed unbuffered RAM and expanded CPU/chipset configuration in the BIOS. Consequentially, Socket F and F 1207 FX are incompatible and require different processors, chipsets, and motherboards. ==Athlon 64 FX models==

Sledgehammer (130 nm SOI) • Stepping level: C0, CG • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 1024 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, AMD64 • Socket 940, 800 MHz HyperTransport (HT800) • Registered DDR-SDRAM required • CPU core voltage (VCore): 1.50 or 1.55 Volts • Power use (TDP): 89 Watt max • First release: September 23, 2003 • Clock rate: 2200 MHz (FX-51, C0), 2400 MHz (FX-53, C0 and CG) Clawhammer (130 nm SOI) • Stepping level: CG • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 1024 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, AMD64 • Socket 939, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.50 Volts • Power use (TDP): 89 Watt (FX-55:104 Watt) • First release: June 1, 2004 • Clock rate: 2400 MHz (FX-53), 2600 MHz (FX-55) San Diego (90 nm SOI) • Stepping level: E4, E6 • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 1024 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit • Socket 939, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.35 or 1.40 Volts • Power use (TDP): 104 Watt max • First release: April 15, 2005 • Clock rate: 2600 MHz (FX-55), 2800 MHz (FX-57) Toledo (90 nm SOI) Dual-core CPU • Stepping level: E6 • L1 cache: 64 + 64 kB (data + instructions), per core • L2 cache: 1024 kB full speed, per core • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit • Socket 939, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.30 or 1.35 Volts • Power use (TDP): 110 Watt max • First release: January 10, 2006 • Clock rate: 2600 MHz (FX-60) Windsor (90 nm SOI) Dual-core CPU • Stepping level: F2, F3 • L1 cache: 64 + 64 kB (data + instructions), per core • L2 cache: 512 - 1024 kB full speed, per core • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit, AMD-V • Socket AM2, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.30 V or 1.40 Volts • Power use (TDP): 125 Watt max • First release: May 23, 2006 • Clock rate: 2000 - 3200 MHz (6400+), 2800 MHz (FX-62) Windsor (90 nm SOI) - Quad FX platform Dual-core, dual CPUs (four cores total) • Stepping level: F3 • L1 cache: 64 + 64 kB (data + instructions), per core • L2 cache: 1024 kB full speed, per core • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit, AMD-V • Socket F (1207 FX), 2000 MHz HyperTransport (HT2000) • CPU core voltage (VCore): 1.35 or 1.40 Volts • Power use (TDP): 125 Watt max per CPU • First release: November 30, 2006 • Clock rate: 2600 MHz (FX-70), 2800 MHz (FX-72), 3000 MHz (FX-74) ==Athlon 64 models==

Clawhammer (130 nm SOI) • Stepping level: C0, CG • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 1024 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, AMD64, Cool'n'Quiet, NX bit (only CG) • Socket 754, 800 MHz HyperTransport (HT800) • Socket 939, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.50 Volts • Power use (TDP): 89 Watt max • First release: September 23, 2003 • Clock rate: 2000–2600 MHz Newcastle (130 nm SOI) Also possible: ClawHammer-512 (Clawhammer with partially disabled L2 cache) • Stepping level: CG • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 512 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, AMD64, Cool'n'Quiet, NX bit • Socket 754, 800 MHz HyperTransport (HT800) • Socket 939, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.50 Volts • Power use (TDP): 89 Watt max • First release: 2004 • Clock rate: 1800–2400 MHz Winchester (90 nm SOI) • Stepping level: D0 • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 512 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, AMD64, Cool'n'Quiet, NX bit • Socket 939, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.40 Volts • Power use (TDP): 67 Watt max • First release: 2004 • Clock rate: 1800–2200 MHz Venice (90 nm SOI) • Stepping level: E3, E6 • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 512 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit • Socket 754, 800 MHz HyperTransport (HT800) • Socket 939, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.35 or 1.40 Volts • Power use (TDP): 89 Watt max • First release: April 4, 2005 • Clock rate: 1800–2400 MHz San Diego (90 nm SOI) • Stepping level: E4, E6 • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 1024 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit • Socket 939, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.35 or 1.40 Volts • Power use (TDP): 89 Watt max • First release: April 15, 2005 • Clock rate: 2200–2600 MHz Manchester (90 nm SOI) • Stepping level: F1 • L1 cache: 2 x 64 + 2 x 64 kB (data + instructions) • L2 cache: 2 x 512 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit • Socket 939, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.35 Volts • Power use (TDP): 89 Watt max • First release: April 15, 2005 • Clock rate: 2200–2600 MHz Orleans (90 nm SOI) • Stepping level: F2, F3 • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 512 kB, 1 MB • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit, AMD-V • Socket AM2, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.25 or 1.40 Volts • Power use (TDP): 62 Watt max • First release: May 23, 2006 • Clock rate: 1800–2600 MHz Lima (65 nm SOI) • Stepping level: G1 • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 512 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit, AMD-V • Socket AM2, 1000 MHz HyperTransport (HT1000) • CPU core voltage (VCore): 1.25, 1.35, or 1.40 Volts • Power use (TDP): 45 Watt max • First release: February 20, 2007 • Clock rate: 2000–2800 MHz ==Athlon Neo==

Huron (65 nm SOI) • Stepping level: G2 • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 512 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit, AMD-V • ASB1 package (BGA), 800 MHz HyperTransport (HT800) • CPU core voltage (VCore): 1.1 Volts • Power use (TDP): 15 Watt max • First release: January 8, 2009 • Clock rate: 1600 MHz Athlon X2 Dual Core Processor L310 • Generation: K8 • 65 nm SOI • Stepping level: G • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: 512 kB, full speed • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, NX bit, AMD-V • ASB1 package (BGA), 800 MHz HyperTransport (HT800) • Power use (TDP): 13 Watt max • PowerNow!: No • P-States: 1 • Clock rate: 1200 MHz Athlon X2 Dual Core Processor L335 • Generation: K8 • 65 nm SOI • Stepping level: G • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: (2*256 kB), full speed • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet(?), NX bit, AMD-V • ASB1 package (BGA), 800 MHz HyperTransport (HT800) • Power use (TDP): 18 Watt max • PowerNow!: Yes • Clock rate: 1600 MHz Turion Neo X2 Dual Core Processor L625 • Generation: K8 • 65 nm SOI • Stepping level: G2 • L1 cache: 64 + 64 kB (data + instructions) • L2 cache: (2*512 kB), full speed • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit, AMD-V • ASB1 package (BGA), 800 MHz HyperTransport (HT800) • Power use (TDP): 18 Watt max • PowerNow!: Yes • Clock rate: 1600 MHz ==Successors==

The Athlon 64 was succeeded by the K10 architecture in 2007, including but not limited to the Phenom and Phenom II processors. These successors feature higher core counts per CPU, and implement Hypertransport 3.0 and Socket AM2+/AM3. As of February 2012, Athlon 64 X2 processors were still available for sale. ==See also==